[llvm] a0eee6c - [SystemZ] Allow symbols in immediate asm operands
Ilya Leoshkevich via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 21 02:09:36 PDT 2023
Author: Ilya Leoshkevich
Date: 2023-07-21T11:09:19+02:00
New Revision: a0eee6c971878b1f2edcc34fb2513e12a04a29ba
URL: https://github.com/llvm/llvm-project/commit/a0eee6c971878b1f2edcc34fb2513e12a04a29ba
DIFF: https://github.com/llvm/llvm-project/commit/a0eee6c971878b1f2edcc34fb2513e12a04a29ba.diff
LOG: [SystemZ] Allow symbols in immediate asm operands
Currently mentioning any symbols in immediate asm operands is not
supported, for example:
error: invalid operand for instruction
lghi %r4,foo_end-foo
The immediate problem is that is*Imm() and print*Operand() functions do
not accept MCExprs, but simply relaxing these checks is not enough:
after symbol addresses are computed, range checks need to run against
resolved values.
Add a number of SystemZ::FixupKind members for each kind of immediate
value and process them in SystemZMCAsmBackend::applyFixup(). Only
perform the range checks, do not change anything.
Adjust the tests: move previously failing cases like the one shown
above out of insn-bad.s.
Reviewed By: uweigand
Differential Revision: https://reviews.llvm.org/D154899
Added:
llvm/test/MC/SystemZ/fixups-bad-z13.s
Modified:
llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.cpp
llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h
llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCObjectWriter.cpp
llvm/lib/Target/SystemZ/SystemZOperands.td
llvm/test/MC/SystemZ/fixups.s
llvm/test/MC/SystemZ/insn-bad-z196.s
llvm/test/MC/SystemZ/insn-bad.s
llvm/test/MC/SystemZ/insn-good-z196.s
llvm/test/MC/SystemZ/insn-good.s
llvm/test/MC/SystemZ/reloc-absolute.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
index 4f8d16b501b845..dc4f2a438c9f7f 100644
--- a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
+++ b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
@@ -237,7 +237,7 @@ class SystemZOperand : public MCParsedAsmOperand {
return Kind == KindImm;
}
bool isImm(int64_t MinValue, int64_t MaxValue) const {
- return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
+ return Kind == KindImm && inRange(Imm, MinValue, MaxValue, true);
}
const MCExpr *getImm() const {
assert(Kind == KindImm && "Not an immediate");
diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.cpp
index 858954d118503e..a32dc9a2e7d5cd 100644
--- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.cpp
+++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.cpp
@@ -83,7 +83,12 @@ void SystemZInstPrinter::printInst(const MCInst *MI, uint64_t Address,
template <unsigned N>
void SystemZInstPrinter::printUImmOperand(const MCInst *MI, int OpNum,
raw_ostream &O) {
- int64_t Value = MI->getOperand(OpNum).getImm();
+ const MCOperand &MO = MI->getOperand(OpNum);
+ if (MO.isExpr()) {
+ O << *MO.getExpr();
+ return;
+ }
+ uint64_t Value = static_cast<uint64_t>(MO.getImm());
assert(isUInt<N>(Value) && "Invalid uimm argument");
O << markup("<imm:") << Value << markup(">");
}
@@ -91,6 +96,11 @@ void SystemZInstPrinter::printUImmOperand(const MCInst *MI, int OpNum,
template <unsigned N>
void SystemZInstPrinter::printSImmOperand(const MCInst *MI, int OpNum,
raw_ostream &O) {
+ const MCOperand &MO = MI->getOperand(OpNum);
+ if (MO.isExpr()) {
+ O << *MO.getExpr();
+ return;
+ }
int64_t Value = MI->getOperand(OpNum).getImm();
assert(isInt<N>(Value) && "Invalid simm argument");
O << markup("<imm:") << Value << markup(">");
diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
index d9f770a399f623..880766a1a23fb0 100644
--- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
+++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
@@ -47,6 +47,13 @@ static uint64_t extractBitsForFixup(MCFixupKind Kind, uint64_t Value,
return (int64_t)Value / 2;
};
+ auto handleImmValue = [&](bool IsSigned, unsigned W) -> uint64_t {
+ if (!(IsSigned ? checkFixupInRange(minIntN(W), maxIntN(W))
+ : checkFixupInRange(0, maxUIntN(W))))
+ return 0;
+ return Value;
+ };
+
switch (unsigned(Kind)) {
case SystemZ::FK_390_PC12DBL:
return handlePCRelFixupValue(12);
@@ -57,22 +64,41 @@ static uint64_t extractBitsForFixup(MCFixupKind Kind, uint64_t Value,
case SystemZ::FK_390_PC32DBL:
return handlePCRelFixupValue(32);
- case SystemZ::FK_390_12:
- if (!checkFixupInRange(0, maxUIntN(12)))
- return 0;
- return Value;
+ case SystemZ::FK_390_TLS_CALL:
+ return 0;
- case SystemZ::FK_390_20: {
- if (!checkFixupInRange(minIntN(20), maxIntN(20)))
- return 0;
+ case SystemZ::FK_390_S8Imm:
+ return handleImmValue(true, 8);
+ case SystemZ::FK_390_S16Imm:
+ return handleImmValue(true, 16);
+ case SystemZ::FK_390_S20Imm: {
+ Value = handleImmValue(true, 20);
+ // S20Imm is used only for signed 20-bit displacements.
// The high byte of a 20 bit displacement value comes first.
uint64_t DLo = Value & 0xfff;
uint64_t DHi = (Value >> 12) & 0xff;
return (DLo << 8) | DHi;
}
-
- case SystemZ::FK_390_TLS_CALL:
- return 0;
+ case SystemZ::FK_390_S32Imm:
+ return handleImmValue(true, 32);
+ case SystemZ::FK_390_U1Imm:
+ return handleImmValue(false, 1);
+ case SystemZ::FK_390_U2Imm:
+ return handleImmValue(false, 2);
+ case SystemZ::FK_390_U3Imm:
+ return handleImmValue(false, 3);
+ case SystemZ::FK_390_U4Imm:
+ return handleImmValue(false, 4);
+ case SystemZ::FK_390_U8Imm:
+ return handleImmValue(false, 8);
+ case SystemZ::FK_390_U12Imm:
+ return handleImmValue(false, 12);
+ case SystemZ::FK_390_U16Imm:
+ return handleImmValue(false, 16);
+ case SystemZ::FK_390_U32Imm:
+ return handleImmValue(false, 32);
+ case SystemZ::FK_390_U48Imm:
+ return handleImmValue(false, 48);
}
llvm_unreachable("Unknown fixup kind!");
@@ -130,16 +156,6 @@ SystemZMCAsmBackend::getFixupKind(StringRef Name) const {
const MCFixupKindInfo &
SystemZMCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
- const static MCFixupKindInfo Infos[SystemZ::NumTargetFixupKinds] = {
- { "FK_390_PC12DBL", 4, 12, MCFixupKindInfo::FKF_IsPCRel },
- { "FK_390_PC16DBL", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
- { "FK_390_PC24DBL", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
- { "FK_390_PC32DBL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
- { "FK_390_TLS_CALL", 0, 0, 0 },
- { "FK_390_12", 4, 12, 0 },
- { "FK_390_20", 4, 20, 0 }
- };
-
// Fixup kinds from .reloc directive are like R_390_NONE. They
// do not require any extra processing.
if (Kind >= FirstLiteralRelocationKind)
@@ -150,7 +166,7 @@ SystemZMCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
"Invalid kind!");
- return Infos[Kind - FirstTargetFixupKind];
+ return SystemZ::MCFixupKindInfos[Kind - FirstTargetFixupKind];
}
bool SystemZMCAsmBackend::shouldForceRelocation(const MCAssembler &,
diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
index a0648a077e2bf9..e453ec60d70cb0 100644
--- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
+++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
@@ -63,27 +63,19 @@ class SystemZMCCodeEmitter : public MCCodeEmitter {
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
- // Return the displacement value for the OpNum operand. If it is a symbol,
- // add a fixup for it and return 0.
- uint64_t getDispOpValue(const MCInst &MI, unsigned OpNum,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI, unsigned OpSize,
- SystemZ::FixupKind Kind) const;
-
- // Called by the TableGen code to get the binary encoding of an address.
- // The index or length, if any, is encoded first, followed by the base,
- // followed by the displacement. In a 20-bit displacement,
- // the low 12 bits are encoded before the high 8 bits.
- template <unsigned N>
+ // Return the encoded immediate value for the OpNum operand. If it is a
+ // symbol, add a fixup for it and return 0.
+ template <SystemZ::FixupKind Kind>
+ uint64_t getImmOpValue(const MCInst &MI, unsigned OpNum,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
+
+ // Called by the TableGen code to get the binary encoding of a length value.
+ // Length values are encoded by subtracting 1 from the actual value.
+ template <SystemZ::FixupKind Kind>
uint64_t getLenEncoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
- uint64_t getDisp12Encoding(const MCInst &MI, unsigned OpNum,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
- uint64_t getDisp20Encoding(const MCInst &MI, unsigned OpNum,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
// Operand OpNum of MI needs a PC-relative fixup of kind Kind at
// Offset bytes from the start of MI. Add the fixup to Fixups
@@ -161,23 +153,26 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
const MCSubtargetInfo &STI) const {
if (MO.isReg())
return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
+ // SystemZAsmParser::parseAnyRegister() produces KindImm when registers are
+ // specified as integers.
if (MO.isImm())
return static_cast<uint64_t>(MO.getImm());
llvm_unreachable("Unexpected operand type!");
}
-uint64_t SystemZMCCodeEmitter::getDispOpValue(const MCInst &MI, unsigned OpNum,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI,
- unsigned OpSize,
- SystemZ::FixupKind Kind) const {
+template <SystemZ::FixupKind Kind>
+uint64_t SystemZMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNum,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNum);
if (MO.isImm())
return static_cast<uint64_t>(MO.getImm());
if (MO.isExpr()) {
unsigned MIBitSize = MCII.get(MI.getOpcode()).getSize() * 8;
uint32_t RawBitOffset = getOperandBitOffset(MI, OpNum, STI);
- uint32_t BitOffset = MIBitSize - RawBitOffset - OpSize;
+ unsigned OpBitSize =
+ SystemZ::MCFixupKindInfos[Kind - FirstTargetFixupKind].TargetSize;
+ uint32_t BitOffset = MIBitSize - RawBitOffset - OpBitSize;
Fixups.push_back(MCFixup::create(BitOffset >> 3, MO.getExpr(),
(MCFixupKind)Kind, MI.getLoc()));
assert(Fixups.size() <= 2 && "More than two memory operands in MI?");
@@ -186,28 +181,12 @@ uint64_t SystemZMCCodeEmitter::getDispOpValue(const MCInst &MI, unsigned OpNum,
llvm_unreachable("Unexpected operand type!");
}
-template <unsigned N>
+template <SystemZ::FixupKind Kind>
uint64_t
SystemZMCCodeEmitter::getLenEncoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
- return getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI) - 1;
-}
-
-uint64_t
-SystemZMCCodeEmitter::getDisp12Encoding(const MCInst &MI, unsigned OpNum,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- return getDispOpValue(MI, OpNum, Fixups, STI, 12,
- SystemZ::FixupKind::FK_390_12);
-}
-
-uint64_t
-SystemZMCCodeEmitter::getDisp20Encoding(const MCInst &MI, unsigned OpNum,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- return getDispOpValue(MI, OpNum, Fixups, STI, 20,
- SystemZ::FixupKind::FK_390_20);
+ return getImmOpValue<Kind>(MI, OpNum, Fixups, STI) - 1;
}
uint64_t
diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h
index 1f62baabb9e7c8..512e51c0f93398 100644
--- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h
+++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h
@@ -10,6 +10,7 @@
#define LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCFIXUPS_H
#include "llvm/MC/MCFixup.h"
+#include "llvm/MC/MCFixupKindInfo.h"
namespace llvm {
namespace SystemZ {
@@ -20,13 +21,46 @@ enum FixupKind {
FK_390_PC24DBL,
FK_390_PC32DBL,
FK_390_TLS_CALL,
- FK_390_12,
- FK_390_20,
+
+ FK_390_S8Imm,
+ FK_390_S16Imm,
+ FK_390_S20Imm,
+ FK_390_S32Imm,
+ FK_390_U1Imm,
+ FK_390_U2Imm,
+ FK_390_U3Imm,
+ FK_390_U4Imm,
+ FK_390_U8Imm,
+ FK_390_U12Imm,
+ FK_390_U16Imm,
+ FK_390_U32Imm,
+ FK_390_U48Imm,
// Marker
LastTargetFixupKind,
NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
};
+
+const static MCFixupKindInfo MCFixupKindInfos[SystemZ::NumTargetFixupKinds] = {
+ {"FK_390_PC12DBL", 4, 12, MCFixupKindInfo::FKF_IsPCRel},
+ {"FK_390_PC16DBL", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
+ {"FK_390_PC24DBL", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
+ {"FK_390_PC32DBL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
+ {"FK_390_TLS_CALL", 0, 0, 0},
+ {"FK_390_S8Imm", 0, 8, 0},
+ {"FK_390_S16Imm", 0, 16, 0},
+ {"FK_390_S20Imm", 4, 20, 0},
+ {"FK_390_S32Imm", 0, 32, 0},
+ {"FK_390_U1Imm", 0, 1, 0},
+ {"FK_390_U2Imm", 0, 2, 0},
+ {"FK_390_U3Imm", 0, 3, 0},
+ {"FK_390_U4Imm", 0, 4, 0},
+ {"FK_390_U8Imm", 0, 8, 0},
+ {"FK_390_U12Imm", 4, 12, 0},
+ {"FK_390_U16Imm", 0, 16, 0},
+ {"FK_390_U32Imm", 0, 32, 0},
+ {"FK_390_U48Imm", 0, 48, 0},
+};
} // end namespace SystemZ
} // end namespace llvm
diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCObjectWriter.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCObjectWriter.cpp
index 0b11468afc523a..9c6a1b6e8af01c 100644
--- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCObjectWriter.cpp
+++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCObjectWriter.cpp
@@ -43,12 +43,24 @@ SystemZObjectWriter::SystemZObjectWriter(uint8_t OSABI)
// Return the relocation type for an absolute value of MCFixupKind Kind.
static unsigned getAbsoluteReloc(MCContext &Ctx, SMLoc Loc, unsigned Kind) {
switch (Kind) {
- case FK_Data_1: return ELF::R_390_8;
- case FK_Data_2: return ELF::R_390_16;
- case FK_Data_4: return ELF::R_390_32;
- case FK_Data_8: return ELF::R_390_64;
- case SystemZ::FK_390_12: return ELF::R_390_12;
- case SystemZ::FK_390_20: return ELF::R_390_20;
+ case FK_Data_1:
+ case SystemZ::FK_390_U8Imm:
+ case SystemZ::FK_390_S8Imm:
+ return ELF::R_390_8;
+ case SystemZ::FK_390_U12Imm:
+ return ELF::R_390_12;
+ case FK_Data_2:
+ case SystemZ::FK_390_U16Imm:
+ case SystemZ::FK_390_S16Imm:
+ return ELF::R_390_16;
+ case SystemZ::FK_390_S20Imm:
+ return ELF::R_390_20;
+ case FK_Data_4:
+ case SystemZ::FK_390_U32Imm:
+ case SystemZ::FK_390_S32Imm:
+ return ELF::R_390_32;
+ case FK_Data_8:
+ return ELF::R_390_64;
}
Ctx.reportError(Loc, "Unsupported absolute address");
return 0;
@@ -57,13 +69,24 @@ static unsigned getAbsoluteReloc(MCContext &Ctx, SMLoc Loc, unsigned Kind) {
// Return the relocation type for a PC-relative value of MCFixupKind Kind.
static unsigned getPCRelReloc(MCContext &Ctx, SMLoc Loc, unsigned Kind) {
switch (Kind) {
- case FK_Data_2: return ELF::R_390_PC16;
- case FK_Data_4: return ELF::R_390_PC32;
- case FK_Data_8: return ELF::R_390_PC64;
- case SystemZ::FK_390_PC12DBL: return ELF::R_390_PC12DBL;
- case SystemZ::FK_390_PC16DBL: return ELF::R_390_PC16DBL;
- case SystemZ::FK_390_PC24DBL: return ELF::R_390_PC24DBL;
- case SystemZ::FK_390_PC32DBL: return ELF::R_390_PC32DBL;
+ case FK_Data_2:
+ case SystemZ::FK_390_U16Imm:
+ case SystemZ::FK_390_S16Imm:
+ return ELF::R_390_PC16;
+ case FK_Data_4:
+ case SystemZ::FK_390_U32Imm:
+ case SystemZ::FK_390_S32Imm:
+ return ELF::R_390_PC32;
+ case FK_Data_8:
+ return ELF::R_390_PC64;
+ case SystemZ::FK_390_PC12DBL:
+ return ELF::R_390_PC12DBL;
+ case SystemZ::FK_390_PC16DBL:
+ return ELF::R_390_PC16DBL;
+ case SystemZ::FK_390_PC24DBL:
+ return ELF::R_390_PC24DBL;
+ case SystemZ::FK_390_PC32DBL:
+ return ELF::R_390_PC32DBL;
}
Ctx.reportError(Loc, "Unsupported PC-relative address");
return 0;
diff --git a/llvm/lib/Target/SystemZ/SystemZOperands.td b/llvm/lib/Target/SystemZ/SystemZOperands.td
index a363d8752d2ab8..c92e0abe38ac9f 100644
--- a/llvm/lib/Target/SystemZ/SystemZOperands.td
+++ b/llvm/lib/Target/SystemZ/SystemZOperands.td
@@ -23,6 +23,7 @@ class ImmediateTLSAsmOperand<string name>
class ImmediateOp<ValueType vt, string asmop> : Operand<vt> {
let PrintMethod = "print"#asmop#"Operand";
+ let EncoderMethod = "getImmOpValue<SystemZ::FK_390_"#asmop#">";
let DecoderMethod = "decode"#asmop#"Operand";
let ParserMatchClass = !cast<AsmOperandClass>(asmop);
let OperandType = "OPERAND_IMMEDIATE";
@@ -509,11 +510,11 @@ class Imm64 : ImmLeaf<i64, [{}]>, Operand<i64> {
}
def imm64 : Imm64;
def len4imm64 : Imm64 {
- let EncoderMethod = "getLenEncoding<4>";
+ let EncoderMethod = "getLenEncoding<SystemZ::FK_390_U4Imm>";
let DecoderMethod = "decodeLenOperand<4>";
}
def len8imm64 : Imm64 {
- let EncoderMethod = "getLenEncoding<8>";
+ let EncoderMethod = "getLenEncoding<SystemZ::FK_390_U8Imm>";
let DecoderMethod = "decodeLenOperand<8>";
}
@@ -590,14 +591,14 @@ def pcrel32 : PCRelAddress<i64, "pcrel32", PCRel32> {
//===----------------------------------------------------------------------===//
// 12-bit displacement operands.
-let EncoderMethod = "getDisp12Encoding",
+let EncoderMethod = "getImmOpValue<SystemZ::FK_390_U12Imm>",
DecoderMethod = "decodeU12ImmOperand" in {
def disp12imm32 : Operand<i32>;
def disp12imm64 : Operand<i64>;
}
// 20-bit displacement operands.
-let EncoderMethod = "getDisp20Encoding",
+let EncoderMethod = "getImmOpValue<SystemZ::FK_390_S20Imm>",
DecoderMethod = "decodeS20ImmOperand" in {
def disp20imm32 : Operand<i32>;
def disp20imm64 : Operand<i64>;
diff --git a/llvm/test/MC/SystemZ/fixups-bad-z13.s b/llvm/test/MC/SystemZ/fixups-bad-z13.s
new file mode 100644
index 00000000000000..f9a5feb493401b
--- /dev/null
+++ b/llvm/test/MC/SystemZ/fixups-bad-z13.s
@@ -0,0 +1,23 @@
+# RUN: not llvm-mc -triple s390x-unknown-unknown -mcpu=z13 -filetype=obj %s 2>&1 | FileCheck %s
+
+ .text
+
+# CHECK: error: Unsupported absolute address
+# CHECK-NEXT: vleg %v0,0,src
+# CHECK-NEXT: ^
+ vleg %v0,0,src
+
+# CHECK: error: Unsupported absolute address
+# CHECK-NEXT: vleih %v0,0,src
+# CHECK-NEXT: ^
+ vleih %v0,0,src
+
+# CHECK: error: Unsupported absolute address
+# CHECK-NEXT: vleif %v0,0,src
+# CHECK-NEXT: ^
+ vleif %v0,0,src
+
+# CHECK: error: Unsupported absolute address
+# CHECK-NEXT: vrepi %v0,0,src
+# CHECK-NEXT: ^
+ vrepi %v0,0,src
diff --git a/llvm/test/MC/SystemZ/fixups.s b/llvm/test/MC/SystemZ/fixups.s
index 77c71e3c987b18..3c2138e9e62144 100644
--- a/llvm/test/MC/SystemZ/fixups.s
+++ b/llvm/test/MC/SystemZ/fixups.s
@@ -4,6 +4,9 @@
# RUN: llvm-mc -triple s390x-unknown-unknown -mcpu=z13 -filetype=obj %s | \
# RUN: llvm-readobj -r - | FileCheck %s -check-prefix=CHECK-REL
+# RUN: llvm-mc -triple s390x-unknown-unknown -mcpu=z13 -filetype=obj %s | \
+# RUN: llvm-objdump -d - | FileCheck %s -check-prefix=CHECK-DIS
+
# CHECK: larl %r14, target # encoding: [0xc0,0xe0,A,A,A,A]
# CHECK-NEXT: # fixup A - offset: 2, value: target+2, kind: FK_390_PC32DBL
# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_PC32DBL target 0x2
@@ -83,101 +86,101 @@
## BD12
# CHECK: vl %v0, src # encoding: [0xe7,0x00,0b0000AAAA,A,0x00,0x06]
-# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_U12Imm
# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_12 src 0x0
.align 16
vl %v0, src
# CHECK: vl %v0, src(%r1) # encoding: [0xe7,0x00,0b0001AAAA,A,0x00,0x06]
-# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_U12Imm
# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_12 src 0x0
.align 16
vl %v0, src(%r1)
# CHECK: .insn vrx,253987186016262,%v0,src(%r1),3 # encoding: [0xe7,0x00,0b0001AAAA,A,0x30,0x06]
-# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_U12Imm
# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_12 src 0x0
.align 16
.insn vrx,0xe70000000006,%v0,src(%r1),3 # vl
## BD20
# CHECK: lmg %r6, %r15, src # encoding: [0xeb,0x6f,0b0000AAAA,A,A,0x04]
-# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_20
+# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_S20Imm
# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_20 src 0x0
.align 16
lmg %r6, %r15, src
# CHECK: lmg %r6, %r15, src(%r1) # encoding: [0xeb,0x6f,0b0001AAAA,A,A,0x04]
-# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_20
+# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_S20Imm
# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_20 src 0x0
.align 16
lmg %r6, %r15, src(%r1)
# CHECK: .insn siy,258385232527441,src(%r15),240 # encoding: [0xeb,0xf0,0b1111AAAA,A,A,0x51]
-# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_20
+# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_S20Imm
# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_20 src 0x0
.align 16
.insn siy,0xeb0000000051,src(%r15),240 # tmy
## BDX12
# CHECK: la %r14, src # encoding: [0x41,0xe0,0b0000AAAA,A]
-# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_U12Imm
# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_12 src 0x0
.align 16
la %r14, src
# CHECK: la %r14, src(%r1) # encoding: [0x41,0xe0,0b0001AAAA,A]
-# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_U12Imm
# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_12 src 0x0
.align 16
la %r14, src(%r1)
# CHECK: la %r14, src(%r1,%r2) # encoding: [0x41,0xe1,0b0010AAAA,A]
-# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_U12Imm
# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_12 src 0x0
.align 16
la %r14, src(%r1, %r2)
# CHECK: .insn vrx,253987186016262,%v2,src(%r2,%r3),3 # encoding: [0xe7,0x22,0b0011AAAA,A,0x30,0x06]
-# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_U12Imm
# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_12 src 0x0
.align 16
.insn vrx,0xe70000000006,%v2,src(%r2, %r3),3 # vl
##BDX20
# CHECK: lg %r14, src # encoding: [0xe3,0xe0,0b0000AAAA,A,A,0x04]
-# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_20
+# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_S20Imm
# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_20 src 0x0
.align 16
lg %r14, src
# CHECK: lg %r14, src(%r1) # encoding: [0xe3,0xe0,0b0001AAAA,A,A,0x04]
-# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_20
+# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_S20Imm
# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_20 src 0x0
.align 16
lg %r14, src(%r1)
# CHECK: lg %r14, src(%r1,%r2) # encoding: [0xe3,0xe1,0b0010AAAA,A,A,0x04]
-# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_20
+# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_S20Imm
# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_20 src 0x0
.align 16
lg %r14, src(%r1, %r2)
# CHECK: .insn rxy,260584255783013,%f1,src(%r2,%r15) # encoding: [0xed,0x12,0b1111AAAA,A,A,0x65]
-# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_20
+# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_S20Imm
# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_20 src 0x0
.align 16
.insn rxy,0xed0000000065,%f1,src(%r2,%r15) # ldy
##BD12L4
# CHECK: tp src(16) # encoding: [0xeb,0xf0,0b0000AAAA,A,0x00,0xc0]
-# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_U12Imm
# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_12 src 0x0
.align 16
tp src(16)
# CHECK: tp src(16,%r1) # encoding: [0xeb,0xf0,0b0001AAAA,A,0x00,0xc0]
-# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_U12Imm
# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_12 src 0x0
.align 16
tp src(16, %r1)
@@ -185,8 +188,8 @@
##BD12L8
#SSa
# CHECK: mvc dst(1,%r1), src(%r1) # encoding: [0xd2,0x00,0b0001AAAA,A,0b0001BBBB,B]
-# CHECK-NEXT: # fixup A - offset: 2, value: dst, kind: FK_390_12
-# CHECK-NEXT: # fixup B - offset: 4, value: src, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: dst, kind: FK_390_U12Imm
+# CHECK-NEXT: # fixup B - offset: 4, value: src, kind: FK_390_U12Imm
# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_12 dst 0x0
# CHECK-REL: 0x{{[0-9A-F]*4}} R_390_12 src 0x0
.align 16
@@ -194,8 +197,8 @@
#SSb
# CHECK: mvo src(16,%r1), src(1,%r2) # encoding: [0xf1,0xf0,0b0001AAAA,A,0b0010BBBB,B]
-# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_12
-# CHECK-NEXT: # fixup B - offset: 4, value: src, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_U12Imm
+# CHECK-NEXT: # fixup B - offset: 4, value: src, kind: FK_390_U12Imm
# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_12 src 0x0
# CHECK-REL: 0x{{[0-9A-F]*4}} R_390_12 src 0x0
.align 16
@@ -203,8 +206,8 @@
#SSc
# CHECK: srp src(1,%r1), src(%r15), 0 # encoding: [0xf0,0x00,0b0001AAAA,A,0b1111BBBB,B]
-# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_12
-# CHECK-NEXT: # fixup B - offset: 4, value: src, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_U12Imm
+# CHECK-NEXT: # fixup B - offset: 4, value: src, kind: FK_390_U12Imm
# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_12 src 0x0
# CHECK-REL: 0x{{[0-9A-F]*4}} R_390_12 src 0x0
.align 16
@@ -213,16 +216,16 @@
##BDR12
#SSd
# CHECK: mvck dst(%r2,%r1), src, %r3 # encoding: [0xd9,0x23,0b0001AAAA,A,0b0000BBBB,B]
-# CHECK-NEXT: # fixup A - offset: 2, value: dst, kind: FK_390_12
-# CHECK-NEXT: # fixup B - offset: 4, value: src, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: dst, kind: FK_390_U12Imm
+# CHECK-NEXT: # fixup B - offset: 4, value: src, kind: FK_390_U12Imm
# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_12 dst 0x0
# CHECK-REL: 0x{{[0-9A-F]*4}} R_390_12 src 0x0
.align 16
mvck dst(%r2,%r1), src, %r3
# CHECK: .insn ss,238594023227392,dst(%r2,%r1),src,%r3 # encoding: [0xd9,0x23,0b0001AAAA,A,0b0000BBBB,B]
-# CHECK-NEXT: # fixup A - offset: 2, value: dst, kind: FK_390_12
-# CHECK-NEXT: # fixup B - offset: 4, value: src, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: dst, kind: FK_390_U12Imm
+# CHECK-NEXT: # fixup B - offset: 4, value: src, kind: FK_390_U12Imm
# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_12 dst 0x0
# CHECK-REL: 0x{{[0-9A-F]*4}} R_390_12 src 0x0
.align 16
@@ -230,8 +233,8 @@
#SSe
# CHECK: lmd %r2, %r4, src1(%r1), src2(%r1) # encoding: [0xef,0x24,0b0001AAAA,A,0b0001BBBB,B]
-# CHECK-NEXT: # fixup A - offset: 2, value: src1, kind: FK_390_12
-# CHECK-NEXT: # fixup B - offset: 4, value: src2, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: src1, kind: FK_390_U12Imm
+# CHECK-NEXT: # fixup B - offset: 4, value: src2, kind: FK_390_U12Imm
# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_12 src1 0x0
# CHECK-REL: 0x{{[0-9A-F]*4}} R_390_12 src2 0x0
.align 16
@@ -239,8 +242,8 @@
#SSf
# CHECK: pka dst(%r15), src(256,%r15) # encoding: [0xe9,0xff,0b1111AAAA,A,0b1111BBBB,B]
-# CHECK-NEXT: # fixup A - offset: 2, value: dst, kind: FK_390_12
-# CHECK-NEXT: # fixup B - offset: 4, value: src, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: dst, kind: FK_390_U12Imm
+# CHECK-NEXT: # fixup B - offset: 4, value: src, kind: FK_390_U12Imm
# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_12 dst 0x0
# CHECK-REL: 0x{{[0-9A-F]*4}} R_390_12 src 0x0
.align 16
@@ -248,16 +251,16 @@
#SSE
# CHECK: strag dst(%r1), src(%r15) # encoding: [0xe5,0x02,0b0001AAAA,A,0b1111BBBB,B]
-# CHECK-NEXT: # fixup A - offset: 2, value: dst, kind: FK_390_12
-# CHECK-NEXT: # fixup B - offset: 4, value: src, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: dst, kind: FK_390_U12Imm
+# CHECK-NEXT: # fixup B - offset: 4, value: src, kind: FK_390_U12Imm
# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_12 dst 0x0
# CHECK-REL: 0x{{[0-9A-F]*4}} R_390_12 src 0x0
.align 16
strag dst(%r1), src(%r15)
# CHECK: .insn sse,251796752695296,dst(%r1),src(%r15) # encoding: [0xe5,0x02,0b0001AAAA,A,0b1111BBBB,B]
-# CHECK-NEXT: # fixup A - offset: 2, value: dst, kind: FK_390_12
-# CHECK-NEXT: # fixup B - offset: 4, value: src, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: dst, kind: FK_390_U12Imm
+# CHECK-NEXT: # fixup B - offset: 4, value: src, kind: FK_390_U12Imm
# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_12 dst 0x0
# CHECK-REL: 0x{{[0-9A-F]*4}} R_390_12 src 0x0
.align 16
@@ -265,16 +268,16 @@
#SSF
# CHECK: ectg src, src(%r15), %r2 # encoding: [0xc8,0x21,0b0000AAAA,A,0b1111BBBB,B]
-# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_12
-# CHECK-NEXT: # fixup B - offset: 4, value: src, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_U12Imm
+# CHECK-NEXT: # fixup B - offset: 4, value: src, kind: FK_390_U12Imm
# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_12 src 0x0
# CHECK-REL: 0x{{[0-9A-F]*4}} R_390_12 src 0x0
.align 16
ectg src, src(%r15), %r2
# CHECK: .insn ssf,219906620522496,src,src(%r15),%r2 # encoding: [0xc8,0x21,0b0000AAAA,A,0b1111BBBB,B]
-# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_12
-# CHECK-NEXT: # fixup B - offset: 4, value: src, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_U12Imm
+# CHECK-NEXT: # fixup B - offset: 4, value: src, kind: FK_390_U12Imm
# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_12 src 0x0
# CHECK-REL: 0x{{[0-9A-F]*4}} R_390_12 src 0x0
.align 16
@@ -282,17 +285,135 @@
##BDV12
# CHECK: vgeg %v0, src(%v0,%r1), 0 # encoding: [0xe7,0x00,0b0001AAAA,A,0x00,0x12]
-# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_U12Imm
# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_12 src 0x0
.align 16
vgeg %v0, src(%v0,%r1), 0
## Fixup for second operand only
# CHECK: mvc 32(8,%r0), src # encoding: [0xd2,0x07,0x00,0x20,0b0000AAAA,A]
-# CHECK-NEXT: # fixup A - offset: 4, value: src, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 4, value: src, kind: FK_390_U12Imm
.align 16
mvc 32(8,%r0),src
+##U8
+# CHECK: cli 0(%r1), src # encoding: [0x95,A,0x10,0x00]
+# CHECK-NEXT: # fixup A - offset: 1, value: src, kind: FK_390_U8Imm
+# CHECK-REL: 0x{{[0-9A-F]+}} R_390_8 src 0x0
+ .align 16
+ cli 0(%r1),src
+
+# CHECK: [[L:\..+]]:
+# CHECK-NEXT: cli 0(%r1), local_u8-[[L]] # encoding: [0x95,A,0x10,0x00]
+# CHECK-NEXT: # fixup A - offset: 1, value: local_u8-[[L]], kind: FK_390_U8Imm
+# CHECK-DIS: 95 04 10 00 cli 0(%r1), 4
+ .align 16
+ cli 0(%r1),local_u8-.
+local_u8:
+
+##S8
+# CHECK: asi 0(%r1), src # encoding: [0xeb,A,0x10,0x00,0x00,0x6a]
+# CHECK-NEXT: # fixup A - offset: 1, value: src, kind: FK_390_S8Imm
+# CHECK-REL: 0x{{[0-9A-F]+}} R_390_8 src 0x0
+ .align 16
+ asi 0(%r1),src
+
+# CHECK: [[L:\..+]]:
+# CHECK-NEXT: asi 0(%r1), local_s8-[[L]] # encoding: [0xeb,A,0x10,0x00,0x00,0x6a]
+# CHECK-NEXT: # fixup A - offset: 1, value: local_s8-[[L]], kind: FK_390_S8Imm
+# CHECK-DIS: eb 06 10 00 00 6a asi 0(%r1), 6
+ .align 16
+ asi 0(%r1),local_s8-.
+local_s8:
+
+##U16
+# CHECK: oill %r1, src # encoding: [0xa5,0x1b,A,A]
+# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_U16Imm
+# CHECK-REL: 0x{{[0-9A-F]+}} R_390_16 src 0x0
+ .align 16
+ oill %r1,src
+
+# CHECK: [[L:\..+]]:
+# CHECK-NEXT: oill %r1, local_u16-[[L]] # encoding: [0xa5,0x1b,A,A]
+# CHECK-NEXT: # fixup A - offset: 2, value: local_u16-[[L]], kind: FK_390_U16Imm
+# CHECK-DIS: a5 1b 00 04 oill %r1, 4
+ .align 16
+ oill %r1,local_u16-.
+local_u16:
+
+# CHECK: [[L:\..+]]:
+# CHECK-NEXT: oill %r1, src-[[L]] # encoding: [0xa5,0x1b,A,A]
+# CHECK-NEXT: # fixup A - offset: 2, value: src-[[L]], kind: FK_390_U16Imm
+# CHECK-REL: 0x{{[0-9A-F]+}} R_390_PC16 src 0x2
+ .align 16
+ oill %r1,src-.
+
+##S16
+# CHECK: lghi %r1, src # encoding: [0xa7,0x19,A,A]
+# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_S16Imm
+# CHECK-REL: 0x{{[0-9A-F]+}} R_390_16 src 0x0
+ .align 16
+ lghi %r1,src
+
+# CHECK: [[L:\..+]]:
+# CHECK-NEXT: lghi %r1, local_s16-[[L]] # encoding: [0xa7,0x19,A,A]
+# CHECK-NEXT: # fixup A - offset: 2, value: local_s16-[[L]], kind: FK_390_S16Imm
+# CHECK-DIS: a7 19 00 04 lghi %r1, 4
+ .align 16
+ lghi %r1,local_s16-.
+local_s16:
+
+# CHECK: [[L:\..+]]:
+# CHECK-NEXT: lghi %r1, src-[[L]] # encoding: [0xa7,0x19,A,A]
+# CHECK-NEXT: # fixup A - offset: 2, value: src-[[L]], kind: FK_390_S16Imm
+# CHECK-REL: 0x{{[0-9A-F]+}} R_390_PC16 src 0x2
+ .align 16
+ lghi %r1,src-.
+
+##U32
+# CHECK: clfi %r1, src # encoding: [0xc2,0x1f,A,A,A,A]
+# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_U32Imm
+# CHECK-REL: 0x{{[0-9A-F]+}} R_390_32 src 0x0
+ .align 16
+ clfi %r1,src
+
+# CHECK: [[L:\..+]]:
+# CHECK-NEXT: clfi %r1, local_u32-[[L]] # encoding: [0xc2,0x1f,A,A,A,A]
+# CHECK-NEXT: # fixup A - offset: 2, value: local_u32-[[L]], kind: FK_390_U32Imm
+# CHECK-DIS: c2 1f 00 00 00 06 clfi %r1, 6
+ .align 16
+ clfi %r1,local_u32-.
+local_u32:
+
+# CHECK: [[L:\..+]]:
+# CHECK: clfi %r1, src-[[L]] # encoding: [0xc2,0x1f,A,A,A,A]
+# CHECK-NEXT: # fixup A - offset: 2, value: src-[[L]], kind: FK_390_U32Imm
+# CHECK-REL: 0x{{[0-9A-F]+}} R_390_PC32 src 0x2
+ .align 16
+ clfi %r1,src-.
+
+##S32
+# CHECK: lgfi %r1, src # encoding: [0xc0,0x11,A,A,A,A]
+# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_S32Imm
+# CHECK-REL: 0x{{[0-9A-F]+}} R_390_32 src 0x0
+ .align 16
+ lgfi %r1,src
+
+# CHECK: [[L:\..+]]:
+# CHECK: lgfi %r1, local_s32-[[L]] # encoding: [0xc0,0x11,A,A,A,A]
+# CHECK-NEXT: # fixup A - offset: 2, value: local_s32-[[L]], kind: FK_390_S32Imm
+# CHECK-DIS: c0 11 00 00 00 06 lgfi %r1, 6
+ .align 16
+ lgfi %r1,local_s32-.
+local_s32:
+
+# CHECK: [[L:\..+]]:
+# CHECK: lgfi %r1, src-[[L]] # encoding: [0xc0,0x11,A,A,A,A]
+# CHECK-NEXT: # fixup A - offset: 2, value: src-[[L]], kind: FK_390_S32Imm
+# CHECK-REL: 0x{{[0-9A-F]+}} R_390_PC32 src 0x2
+ .align 16
+ lgfi %r1,src-.
+
# Data relocs
# llvm-mc does not show any "encoding" string for data, so we just check the relocs
diff --git a/llvm/test/MC/SystemZ/insn-bad-z196.s b/llvm/test/MC/SystemZ/insn-bad-z196.s
index 7ac5dd9f3f9e7d..3d58ff61b42e81 100644
--- a/llvm/test/MC/SystemZ/insn-bad-z196.s
+++ b/llvm/test/MC/SystemZ/insn-bad-z196.s
@@ -16,23 +16,17 @@
#CHECK: aghik %r0, %r1, -32769
#CHECK: error: invalid operand
#CHECK: aghik %r0, %r1, 32768
-#CHECK: error: invalid operand
-#CHECK: aghik %r0, %r1, foo
aghik %r0, %r1, -32769
aghik %r0, %r1, 32768
- aghik %r0, %r1, foo
#CHECK: error: invalid operand
#CHECK: ahik %r0, %r1, -32769
#CHECK: error: invalid operand
#CHECK: ahik %r0, %r1, 32768
-#CHECK: error: invalid operand
-#CHECK: ahik %r0, %r1, foo
ahik %r0, %r1, -32769
ahik %r0, %r1, 32768
- ahik %r0, %r1, foo
#CHECK: error: invalid operand
#CHECK: aih %r0, (-1 << 31) - 1
diff --git a/llvm/test/MC/SystemZ/insn-bad.s b/llvm/test/MC/SystemZ/insn-bad.s
index b0a12ab5b972e8..6f94731fa0871d 100644
--- a/llvm/test/MC/SystemZ/insn-bad.s
+++ b/llvm/test/MC/SystemZ/insn-bad.s
@@ -85,12 +85,9 @@
#CHECK: aghi %r0, -32769
#CHECK: error: invalid operand
#CHECK: aghi %r0, 32768
-#CHECK: error: invalid operand
-#CHECK: aghi %r0, foo
aghi %r0, -32769
aghi %r0, 32768
- aghi %r0, foo
#CHECK: error: instruction requires: distinct-ops
#CHECK: aghik %r1, %r2, 3
@@ -141,12 +138,9 @@
#CHECK: ahi %r0, -32769
#CHECK: error: invalid operand
#CHECK: ahi %r0, 32768
-#CHECK: error: invalid operand
-#CHECK: ahi %r0, foo
ahi %r0, -32769
ahi %r0, 32768
- ahi %r0, foo
#CHECK: error: instruction requires: distinct-ops
#CHECK: ahik %r1, %r2, 3
@@ -626,14 +620,11 @@
jlo label
jlno label
-#CHECK: error: invalid operand
-#CHECK: brc foo, bar
#CHECK: error: invalid operand
#CHECK: brc -1, bar
#CHECK: error: invalid operand
#CHECK: brc 16, bar
- brc foo, bar
brc -1, bar
brc 16, bar
@@ -668,14 +659,11 @@
#CHECK: jlnop label
jlnop label
-#CHECK: error: invalid operand
-#CHECK: brcl foo, bar
#CHECK: error: invalid operand
#CHECK: brcl -1, bar
#CHECK: error: invalid operand
#CHECK: brcl 16, bar
- brcl foo, bar
brcl -1, bar
brcl 16, bar
@@ -1184,12 +1172,9 @@
#CHECK: cghi %r0, -32769
#CHECK: error: invalid operand
#CHECK: cghi %r0, 32768
-#CHECK: error: invalid operand
-#CHECK: cghi %r0, foo
cghi %r0, -32769
cghi %r0, 32768
- cghi %r0, foo
#CHECK: error: offset out of range
#CHECK: cghrl %r0, -0x1000000002
@@ -1392,12 +1377,9 @@
#CHECK: chi %r0, -32769
#CHECK: error: invalid operand
#CHECK: chi %r0, 32768
-#CHECK: error: invalid operand
-#CHECK: chi %r0, foo
chi %r0, -32769
chi %r0, 32768
- chi %r0, foo
#CHECK: error: instruction requires: high-word
#CHECK: chlr %r0, %r0
@@ -3546,12 +3528,9 @@
#CHECK: lghi %r0, -32769
#CHECK: error: invalid operand
#CHECK: lghi %r0, 32768
-#CHECK: error: invalid operand
-#CHECK: lghi %r0, foo
lghi %r0, -32769
lghi %r0, 32768
- lghi %r0, foo
#CHECK: error: offset out of range
#CHECK: lghrl %r0, -0x1000000002
@@ -3598,12 +3577,9 @@
#CHECK: lhi %r0, -32769
#CHECK: error: invalid operand
#CHECK: lhi %r0, 32768
-#CHECK: error: invalid operand
-#CHECK: lhi %r0, foo
lhi %r0, -32769
lhi %r0, 32768
- lhi %r0, foo
#CHECK: error: offset out of range
#CHECK: lhrl %r0, -0x1000000002
@@ -4321,12 +4297,9 @@
#CHECK: mghi %r0, -32769
#CHECK: error: invalid operand
#CHECK: mghi %r0, 32768
-#CHECK: error: invalid operand
-#CHECK: mghi %r0, foo
mghi %r0, -32769
mghi %r0, 32768
- mghi %r0, foo
#CHECK: error: invalid operand
#CHECK: mh %r0, -1
@@ -4340,12 +4313,9 @@
#CHECK: mhi %r0, -32769
#CHECK: error: invalid operand
#CHECK: mhi %r0, 32768
-#CHECK: error: invalid operand
-#CHECK: mhi %r0, foo
mhi %r0, -32769
mhi %r0, 32768
- mhi %r0, foo
#CHECK: error: invalid operand
#CHECK: mhy %r0, -524289
diff --git a/llvm/test/MC/SystemZ/insn-good-z196.s b/llvm/test/MC/SystemZ/insn-good-z196.s
index 7faa04a071cc38..fc90b18e66d8f1 100644
--- a/llvm/test/MC/SystemZ/insn-good-z196.s
+++ b/llvm/test/MC/SystemZ/insn-good-z196.s
@@ -24,6 +24,7 @@
#CHECK: aghik %r0, %r15, 0 # encoding: [0xec,0x0f,0x00,0x00,0x00,0xd9]
#CHECK: aghik %r15, %r0, 0 # encoding: [0xec,0xf0,0x00,0x00,0x00,0xd9]
#CHECK: aghik %r7, %r8, -16 # encoding: [0xec,0x78,0xff,0xf0,0x00,0xd9]
+#CHECK: aghik %r0, %r1, foo # encoding: [0xec,0x01,A,A,0x00,0xd9]
aghik %r0, %r0, -32768
aghik %r0, %r0, -1
@@ -33,6 +34,7 @@
aghik %r0, %r15, 0
aghik %r15, %r0, 0
aghik %r7, %r8, -16
+ aghik %r0, %r1, foo
#CHECK: agrk %r0, %r0, %r0 # encoding: [0xb9,0xe8,0x00,0x00]
#CHECK: agrk %r0, %r0, %r15 # encoding: [0xb9,0xe8,0xf0,0x00]
@@ -78,6 +80,7 @@
#CHECK: ahik %r0, %r15, 0 # encoding: [0xec,0x0f,0x00,0x00,0x00,0xd8]
#CHECK: ahik %r15, %r0, 0 # encoding: [0xec,0xf0,0x00,0x00,0x00,0xd8]
#CHECK: ahik %r7, %r8, -16 # encoding: [0xec,0x78,0xff,0xf0,0x00,0xd8]
+#CHECK: ahik %r0, %r1, foo # encoding: [0xec,0x01,A,A,0x00,0xd8]
ahik %r0, %r0, -32768
ahik %r0, %r0, -1
@@ -87,6 +90,7 @@
ahik %r0, %r15, 0
ahik %r15, %r0, 0
ahik %r7, %r8, -16
+ ahik %r0, %r1, foo
#CHECK: aih %r0, -2147483648 # encoding: [0xcc,0x08,0x80,0x00,0x00,0x00]
#CHECK: aih %r0, -1 # encoding: [0xcc,0x08,0xff,0xff,0xff,0xff]
diff --git a/llvm/test/MC/SystemZ/insn-good.s b/llvm/test/MC/SystemZ/insn-good.s
index d837b60e72981d..34961b3d3f7723 100644
--- a/llvm/test/MC/SystemZ/insn-good.s
+++ b/llvm/test/MC/SystemZ/insn-good.s
@@ -236,6 +236,7 @@
#CHECK: aghi %r0, 1 # encoding: [0xa7,0x0b,0x00,0x01]
#CHECK: aghi %r0, 32767 # encoding: [0xa7,0x0b,0x7f,0xff]
#CHECK: aghi %r15, 0 # encoding: [0xa7,0xfb,0x00,0x00]
+#CHECK: aghi %r0, foo # encoding: [0xa7,0x0b,A,A]
aghi %r0, -32768
aghi %r0, -1
@@ -243,6 +244,7 @@
aghi %r0, 1
aghi %r0, 32767
aghi %r15, 0
+ aghi %r0, foo
#CHECK: agr %r0, %r0 # encoding: [0xb9,0x08,0x00,0x00]
#CHECK: agr %r0, %r15 # encoding: [0xb9,0x08,0x00,0x0f]
@@ -304,6 +306,7 @@
#CHECK: ahi %r0, 1 # encoding: [0xa7,0x0a,0x00,0x01]
#CHECK: ahi %r0, 32767 # encoding: [0xa7,0x0a,0x7f,0xff]
#CHECK: ahi %r15, 0 # encoding: [0xa7,0xfa,0x00,0x00]
+#CHECK: ahi %r0, foo # encoding: [0xa7,0x0a,A,A]
ahi %r0, -32768
ahi %r0, -1
@@ -311,6 +314,7 @@
ahi %r0, 1
ahi %r0, 32767
ahi %r15, 0
+ ahi %r0, foo
#CHECK: ahy %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x7a]
#CHECK: ahy %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x7a]
@@ -3425,6 +3429,7 @@
#CHECK: cghi %r0, 1 # encoding: [0xa7,0x0f,0x00,0x01]
#CHECK: cghi %r0, 32767 # encoding: [0xa7,0x0f,0x7f,0xff]
#CHECK: cghi %r15, 0 # encoding: [0xa7,0xff,0x00,0x00]
+#CHECK: cghi %r0, foo # encoding: [0xa7,0x0f,A,A]
cghi %r0, -32768
cghi %r0, -1
@@ -3432,6 +3437,7 @@
cghi %r0, 1
cghi %r0, 32767
cghi %r15, 0
+ cghi %r0, foo
#CHECK: cghrl %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc6,0x04,A,A,A,A]
#CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL
@@ -4286,6 +4292,7 @@
#CHECK: chi %r0, 1 # encoding: [0xa7,0x0e,0x00,0x01]
#CHECK: chi %r0, 32767 # encoding: [0xa7,0x0e,0x7f,0xff]
#CHECK: chi %r15, 0 # encoding: [0xa7,0xfe,0x00,0x00]
+#CHECK: chi %r0, foo # encoding: [0xa7,0x0e,A,A]
chi %r0, -32768
chi %r0, -1
@@ -4293,6 +4300,7 @@
chi %r0, 1
chi %r0, 32767
chi %r15, 0
+ chi %r0, foo
#CHECK: chrl %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc6,0x05,A,A,A,A]
#CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL
@@ -9608,6 +9616,7 @@
#CHECK: lghi %r0, 1 # encoding: [0xa7,0x09,0x00,0x01]
#CHECK: lghi %r0, 32767 # encoding: [0xa7,0x09,0x7f,0xff]
#CHECK: lghi %r15, 0 # encoding: [0xa7,0xf9,0x00,0x00]
+#CHECK: lghi %r14, foo # encoding: [0xa7,0xe9,A,A]
lghi %r0, -32768
lghi %r0, -1
@@ -9615,6 +9624,7 @@
lghi %r0, 1
lghi %r0, 32767
lghi %r15, 0
+ lghi %r14, foo
#CHECK: lghr %r0, %r15 # encoding: [0xb9,0x07,0x00,0x0f]
#CHECK: lghr %r7, %r8 # encoding: [0xb9,0x07,0x00,0x78]
@@ -9730,6 +9740,7 @@
#CHECK: lhi %r0, 1 # encoding: [0xa7,0x08,0x00,0x01]
#CHECK: lhi %r0, 32767 # encoding: [0xa7,0x08,0x7f,0xff]
#CHECK: lhi %r15, 0 # encoding: [0xa7,0xf8,0x00,0x00]
+#CHECK: lhi %r0, foo # encoding: [0xa7,0x08,A,A]
lhi %r0, -32768
lhi %r0, -1
@@ -9737,6 +9748,7 @@
lhi %r0, 1
lhi %r0, 32767
lhi %r15, 0
+ lhi %r0, foo
#CHECK: lhr %r0, %r15 # encoding: [0xb9,0x27,0x00,0x0f]
#CHECK: lhr %r7, %r8 # encoding: [0xb9,0x27,0x00,0x78]
@@ -11641,6 +11653,7 @@
#CHECK: mghi %r0, 1 # encoding: [0xa7,0x0d,0x00,0x01]
#CHECK: mghi %r0, 32767 # encoding: [0xa7,0x0d,0x7f,0xff]
#CHECK: mghi %r15, 0 # encoding: [0xa7,0xfd,0x00,0x00]
+#CHECK: mghi %r0, foo # encoding: [0xa7,0x0d,A,A]
mghi %r0, -32768
mghi %r0, -1
@@ -11648,6 +11661,7 @@
mghi %r0, 1
mghi %r0, 32767
mghi %r15, 0
+ mghi %r0, foo
#CHECK: mh %r0, 0 # encoding: [0x4c,0x00,0x00,0x00]
#CHECK: mh %r0, 4095 # encoding: [0x4c,0x00,0x0f,0xff]
@@ -11671,6 +11685,7 @@
#CHECK: mhi %r0, 1 # encoding: [0xa7,0x0c,0x00,0x01]
#CHECK: mhi %r0, 32767 # encoding: [0xa7,0x0c,0x7f,0xff]
#CHECK: mhi %r15, 0 # encoding: [0xa7,0xfc,0x00,0x00]
+#CHECK: mhi %r0, foo # encoding: [0xa7,0x0c,A,A]
mhi %r0, -32768
mhi %r0, -1
@@ -11678,6 +11693,7 @@
mhi %r0, 1
mhi %r0, 32767
mhi %r15, 0
+ mhi %r0, foo
#CHECK: mhy %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x7c]
#CHECK: mhy %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x7c]
diff --git a/llvm/test/MC/SystemZ/reloc-absolute.s b/llvm/test/MC/SystemZ/reloc-absolute.s
index 8b08af013e3d6f..0369be8183ae2f 100644
--- a/llvm/test/MC/SystemZ/reloc-absolute.s
+++ b/llvm/test/MC/SystemZ/reloc-absolute.s
@@ -9,101 +9,101 @@
## BD12
# CHECK: vl %v0, b-a # encoding: [0xe7,0x00,0b0000AAAA,A,0x00,0x06]
-# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_U12Imm
# CHECK-REL: e7 00 00 04 00 06 vl %v0, 4
.align 16
vl %v0, b-a
# CHECK: vl %v0, b-a(%r1) # encoding: [0xe7,0x00,0b0001AAAA,A,0x00,0x06]
-# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_U12Imm
# CHECK-REL: e7 00 10 04 00 06 vl %v0, 4(%r1)
.align 16
vl %v0, b-a(%r1)
# CHECK: .insn vrx,253987186016262,%v0,b-a(%r1),3 # encoding: [0xe7,0x00,0b0001AAAA,A,0x30,0x06]
-# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_U12Imm
# CHECK-REL: e7 00 10 04 30 06 vl %v0, 4(%r1), 3
.align 16
.insn vrx,0xe70000000006,%v0,b-a(%r1),3 # vl
## BD20
# CHECK: lmg %r6, %r15, b-a # encoding: [0xeb,0x6f,0b0000AAAA,A,A,0x04]
-# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_20
+# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_S20Imm
# CHECK-REL: eb 6f 00 04 00 04 lmg %r6, %r15, 4
.align 16
lmg %r6, %r15, b-a
# CHECK: lmg %r6, %r15, b-a(%r1) # encoding: [0xeb,0x6f,0b0001AAAA,A,A,0x04]
-# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_20
+# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_S20Imm
# CHECK-REL: eb 6f 10 04 00 04 lmg %r6, %r15, 4(%r1)
.align 16
lmg %r6, %r15, b-a(%r1)
# CHECK: .insn siy,258385232527441,b-a(%r15),240 # encoding: [0xeb,0xf0,0b1111AAAA,A,A,0x51]
-# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_20
+# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_S20Imm
# CHECK-REL: eb f0 f0 04 00 51 tmy 4(%r15), 240
.align 16
.insn siy,0xeb0000000051,b-a(%r15),240 # tmy
## BDX12
# CHECK: la %r14, b-a # encoding: [0x41,0xe0,0b0000AAAA,A]
-# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_U12Imm
# CHECK-REL: 41 e0 00 04 la %r14, 4
.align 16
la %r14, b-a
# CHECK: la %r14, b-a(%r1) # encoding: [0x41,0xe0,0b0001AAAA,A]
-# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_U12Imm
# CHECK-REL: 41 e0 10 04 la %r14, 4(%r1)
.align 16
la %r14, b-a(%r1)
# CHECK: la %r14, b-a(%r1,%r2) # encoding: [0x41,0xe1,0b0010AAAA,A]
-# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_U12Imm
# CHECK-REL: 41 e1 20 04 la %r14, 4(%r1,%r2)
.align 16
la %r14, b-a(%r1, %r2)
# CHECK: .insn vrx,253987186016262,%v2,b-a(%r2,%r3),3 # encoding: [0xe7,0x22,0b0011AAAA,A,0x30,0x06]
-# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_U12Imm
# CHECK-REL: e7 22 30 04 30 06 vl %v2, 4(%r2,%r3), 3
.align 16
.insn vrx,0xe70000000006,%v2,b-a(%r2, %r3),3 # vl
##BDX20
# CHECK: lg %r14, b-a # encoding: [0xe3,0xe0,0b0000AAAA,A,A,0x04]
-# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_20
+# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_S20Imm
# CHECK-REL: e3 e0 00 04 00 04 lg %r14, 4
.align 16
lg %r14, b-a
# CHECK: lg %r14, b-a(%r1) # encoding: [0xe3,0xe0,0b0001AAAA,A,A,0x04]
-# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_20
+# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_S20Imm
# CHECK-REL: e3 e0 10 04 00 04 lg %r14, 4(%r1)
.align 16
lg %r14, b-a(%r1)
# CHECK: lg %r14, b-a(%r1,%r2) # encoding: [0xe3,0xe1,0b0010AAAA,A,A,0x04]
-# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_20
+# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_S20Imm
# CHECK-REL: e3 e1 20 04 00 04 lg %r14, 4(%r1,%r2)
.align 16
lg %r14, b-a(%r1, %r2)
# CHECK: .insn rxy,260584255783013,%f1,b-a(%r2,%r15) # encoding: [0xed,0x12,0b1111AAAA,A,A,0x65]
-# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_20
+# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_S20Imm
# CHECK-REL: ed 12 f0 04 00 65 ldy %f1, 4(%r2,%r15)
.align 16
.insn rxy,0xed0000000065,%f1,b-a(%r2,%r15) # ldy
##BD12L4
# CHECK: tp b-a(16) # encoding: [0xeb,0xf0,0b0000AAAA,A,0x00,0xc0]
-# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_U12Imm
# CHECK-REL: eb f0 00 04 00 c0 tp 4(16)
.align 16
tp b-a(16)
# CHECK: tp b-a(16,%r1) # encoding: [0xeb,0xf0,0b0001AAAA,A,0x00,0xc0]
-# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_U12Imm
# CHECK-REL: eb f0 10 04 00 c0 tp 4(16,%r1)
.align 16
tp b-a(16, %r1)
@@ -111,24 +111,24 @@
##BD12L8
#SSa
# CHECK: mvc c-b(1,%r1), b-a(%r1) # encoding: [0xd2,0x00,0b0001AAAA,A,0b0001BBBB,B]
-# CHECK-NEXT: # fixup A - offset: 2, value: c-b, kind: FK_390_12
-# CHECK-NEXT: # fixup B - offset: 4, value: b-a, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: c-b, kind: FK_390_U12Imm
+# CHECK-NEXT: # fixup B - offset: 4, value: b-a, kind: FK_390_U12Imm
# CHECK-REL: d2 00 10 08 10 04 mvc 8(1,%r1), 4(%r1)
.align 16
mvc c-b(1,%r1), b-a(%r1)
#SSb
# CHECK: mvo c-b(16,%r1), b-a(1,%r2) # encoding: [0xf1,0xf0,0b0001AAAA,A,0b0010BBBB,B]
-# CHECK-NEXT: # fixup A - offset: 2, value: c-b, kind: FK_390_12
-# CHECK-NEXT: # fixup B - offset: 4, value: b-a, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: c-b, kind: FK_390_U12Imm
+# CHECK-NEXT: # fixup B - offset: 4, value: b-a, kind: FK_390_U12Imm
# CHECK-REL: f1 f0 10 08 20 04 mvo 8(16,%r1), 4(1,%r2)
.align 16
mvo c-b(16,%r1), b-a(1,%r2)
#SSc
# CHECK: srp b-a(1,%r1), b-a(%r15), 0 # encoding: [0xf0,0x00,0b0001AAAA,A,0b1111BBBB,B]
-# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_12
-# CHECK-NEXT: # fixup B - offset: 4, value: b-a, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_U12Imm
+# CHECK-NEXT: # fixup B - offset: 4, value: b-a, kind: FK_390_U12Imm
# CHECK-REL: f0 00 10 04 f0 04 srp 4(1,%r1), 4(%r15), 0
.align 16
srp b-a(1,%r1), b-a(%r15), 0
@@ -136,68 +136,68 @@
##BDR12
#SSd
# CHECK: mvck c-b(%r2,%r1), b-a, %r3 # encoding: [0xd9,0x23,0b0001AAAA,A,0b0000BBBB,B]
-# CHECK-NEXT: # fixup A - offset: 2, value: c-b, kind: FK_390_12
-# CHECK-NEXT: # fixup B - offset: 4, value: b-a, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: c-b, kind: FK_390_U12Imm
+# CHECK-NEXT: # fixup B - offset: 4, value: b-a, kind: FK_390_U12Imm
# CHECK-REL: d9 23 10 08 00 04 mvck 8(%r2,%r1), 4, %r3
.align 16
mvck c-b(%r2,%r1), b-a, %r3
# CHECK: .insn ss,238594023227392,c-b(%r2,%r1),b-a,%r3 # encoding: [0xd9,0x23,0b0001AAAA,A,0b0000BBBB,B]
-# CHECK-NEXT: # fixup A - offset: 2, value: c-b, kind: FK_390_12
-# CHECK-NEXT: # fixup B - offset: 4, value: b-a, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: c-b, kind: FK_390_U12Imm
+# CHECK-NEXT: # fixup B - offset: 4, value: b-a, kind: FK_390_U12Imm
# CHECK-REL: d9 23 10 08 00 04 mvck 8(%r2,%r1), 4, %r3
.align 16
.insn ss,0xd90000000000,c-b(%r2,%r1),b-a,%r3 # mvck
#SSe
# CHECK: lmd %r2, %r4, b-a(%r1), c-b(%r1) # encoding: [0xef,0x24,0b0001AAAA,A,0b0001BBBB,B]
-# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_12
-# CHECK-NEXT: # fixup B - offset: 4, value: c-b, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_U12Imm
+# CHECK-NEXT: # fixup B - offset: 4, value: c-b, kind: FK_390_U12Imm
# CHECK-REL: ef 24 10 04 10 08 lmd %r2, %r4, 4(%r1), 8(%r1)
.align 16
lmd %r2, %r4, b-a(%r1), c-b(%r1)
#SSf
# CHECK: pka c-b(%r15), b-a(256,%r15) # encoding: [0xe9,0xff,0b1111AAAA,A,0b1111BBBB,B]
-# CHECK-NEXT: # fixup A - offset: 2, value: c-b, kind: FK_390_12
-# CHECK-NEXT: # fixup B - offset: 4, value: b-a, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: c-b, kind: FK_390_U12Imm
+# CHECK-NEXT: # fixup B - offset: 4, value: b-a, kind: FK_390_U12Imm
# CHECK-REL: e9 ff f0 08 f0 04 pka 8(%r15), 4(256,%r15)
.align 16
pka c-b(%r15), b-a(256,%r15)
#SSE
# CHECK: strag c-b(%r1), b-a(%r15) # encoding: [0xe5,0x02,0b0001AAAA,A,0b1111BBBB,B]
-# CHECK-NEXT: # fixup A - offset: 2, value: c-b, kind: FK_390_12
-# CHECK-NEXT: # fixup B - offset: 4, value: b-a, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: c-b, kind: FK_390_U12Imm
+# CHECK-NEXT: # fixup B - offset: 4, value: b-a, kind: FK_390_U12Imm
# CHECK-REL: e5 02 10 08 f0 04 strag 8(%r1), 4(%r15)
.align 16
strag c-b(%r1), b-a(%r15)
# CHECK: .insn sse,251796752695296,c-b(%r1),b-a(%r15) # encoding: [0xe5,0x02,0b0001AAAA,A,0b1111BBBB,B]
-# CHECK-NEXT: # fixup A - offset: 2, value: c-b, kind: FK_390_12
-# CHECK-NEXT: # fixup B - offset: 4, value: b-a, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: c-b, kind: FK_390_U12Imm
+# CHECK-NEXT: # fixup B - offset: 4, value: b-a, kind: FK_390_U12Imm
# CHECK-REL: e5 02 10 08 f0 04 strag 8(%r1), 4(%r15)
.align 16
.insn sse,0xe50200000000,c-b(%r1),b-a(%r15) # strag
#SSF
# CHECK: ectg b-a, b-a(%r15), %r2 # encoding: [0xc8,0x21,0b0000AAAA,A,0b1111BBBB,B]
-# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_12
-# CHECK-NEXT: # fixup B - offset: 4, value: b-a, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_U12Imm
+# CHECK-NEXT: # fixup B - offset: 4, value: b-a, kind: FK_390_U12Imm
# CHECK-REL: c8 21 00 04 f0 04 ectg 4, 4(%r15), %r2
.align 16
ectg b-a, b-a(%r15), %r2
# CHECK: .insn ssf,219906620522496,b-a,b-a(%r15),%r2 # encoding: [0xc8,0x21,0b0000AAAA,A,0b1111BBBB,B]
-# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_12
-# CHECK-NEXT: # fixup B - offset: 4, value: b-a, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_U12Imm
+# CHECK-NEXT: # fixup B - offset: 4, value: b-a, kind: FK_390_U12Imm
# CHECK-REL: c8 21 00 04 f0 04 ectg 4, 4(%r15), %r2
.align 16
.insn ssf,0xc80100000000,b-a,b-a(%r15),%r2 # ectg
##BDV12
# CHECK: vgeg %v0, b-a(%v0,%r1), 0 # encoding: [0xe7,0x00,0b0001AAAA,A,0x00,0x12]
-# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_12
+# CHECK-NEXT: # fixup A - offset: 2, value: b-a, kind: FK_390_U12Imm
# CHECK-REL: e7 00 10 04 00 12 vgeg %v0, 4(%v0,%r1), 0
.align 16
vgeg %v0, b-a(%v0,%r1), 0
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