[PATCH] D155772: [RISCV][GlobalISel] Legalize bitshift instructions for narrow types

[Thorsten via Phabricator via llvm-commits]

tschuett added inline comments.


================
Comment at: llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp:34
+      .legalFor({XLenLLT, XLenLLT})
+      .clampScalar(1, XLenLLT, XLenLLT)
+      .clampScalar(0, XLenLLT, XLenLLT);
----------------
You claim: " types narrower and upto XLen". But you clamp to XLenLLT?


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Comment at: llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-ashr.mir:21
+    %3:_(s8) = G_TRUNC %1(s32)
+    %4:_(s8) = G_ASHR %3, %4
+    %5:_(s32) = G_ANYEXT %4(s8)
----------------
Input and output are %4?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155772/new/

https://reviews.llvm.org/D155772