[PATCH] D155772: [RISCV][GlobalISel] Legalize bitshift instructions for narrow types

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Jul 20 22:06:48 PDT 2023


craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp:38
+  // Extensions
+  auto ExtLegalFunc = [=](const LegalityQuery &Query) {
+    unsigned DstSize = Query.Types[0].getSizeInBits();
----------------
arsenm wrote:
> Do you actually need to permit anything besides XLenVT? I would hope if all of these were illegal the artifact combiner would eliminate all the casts in your examples
I had tried to help Nitin with this. I think it wasn't working with just `.clampScalar(0, XLenLLT, XLenLLT);`. The code here was taken from AArch64 and modified to XLen.


================
Comment at: llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp:59
+      .legalIf(ExtLegalFunc)
+      .clampScalar(0, XLenLLT, XLenLLT); // Just for XLen, others are handled.
+
----------------
This should be 2*XLen. The AArch64 code says 128 here.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155772/new/

https://reviews.llvm.org/D155772



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