[PATCH] D155872: [AArch64] Add vselect(fmin/fmax) SVE patterns

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: Allen, paulwalker-arm, sdesmalen, david-arm.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: All.
dmgreen requested review of this revision.
Herald added a project: LLVM.

For both minnum/maxnum and minimum/maximum, this adds tablegen patterns for vselect(fmin/fmax), creating a predicate fminnm/fmaxnm/fmin/fmax nodes.


https://reviews.llvm.org/D155872

Files:
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll

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