[llvm] 24bb36e - [RISCV] Remove Opcode field from RVInst. Assign Inst{6-0} directly. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 20 08:18:44 PDT 2023
Author: Craig Topper
Date: 2023-07-20T08:18:06-07:00
New Revision: 24bb36e58eac6da7f8437c1a9ff8ad96e10578ca
URL: https://github.com/llvm/llvm-project/commit/24bb36e58eac6da7f8437c1a9ff8ad96e10578ca
DIFF: https://github.com/llvm/llvm-project/commit/24bb36e58eac6da7f8437c1a9ff8ad96e10578ca.diff
LOG: [RISCV] Remove Opcode field from RVInst. Assign Inst{6-0} directly. NFC
Most places assign Opcode right after assigning every other bit in
Inst. I don't think treating Opcode separately adds much value. It
doesn't hide what bits belong to the opcode since every other bits is
listed.
This makes RVInst consistent with RVInst16 subclasss which already
assign Inst{1-0} directly.
Reviewed By: asb, wangpc
Differential Revision: https://reviews.llvm.org/D155797
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrFormats.td
llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
index 022f7d1fcf6c9c..828de0714381bc 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -224,10 +224,6 @@ class RVInst<dag outs, dag ins, string opcodestr, string argstr,
// to build the decode table.
field bits<32> SoftFail = 0;
let Size = 4;
-
- bits<7> Opcode = 0;
-
- let Inst{6-0} = Opcode;
}
// Pseudo instructions
@@ -289,7 +285,7 @@ class RVInstR<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode, dag outs,
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = rd;
- let Opcode = opcode.Value;
+ let Inst{6-0} = opcode.Value;
}
class RVInstR4<bits<2> funct2, bits<3> funct3, RISCVOpcode opcode, dag outs,
@@ -306,7 +302,7 @@ class RVInstR4<bits<2> funct2, bits<3> funct3, RISCVOpcode opcode, dag outs,
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = rd;
- let Opcode = opcode.Value;
+ let Inst{6-0} = opcode.Value;
}
class RVInstR4Frm<bits<2> funct2, RISCVOpcode opcode, dag outs, dag ins,
@@ -324,7 +320,7 @@ class RVInstR4Frm<bits<2> funct2, RISCVOpcode opcode, dag outs, dag ins,
let Inst{19-15} = rs1;
let Inst{14-12} = frm;
let Inst{11-7} = rd;
- let Opcode = opcode.Value;
+ let Inst{6-0} = opcode.Value;
}
class RVInstRAtomic<bits<5> funct5, bit aq, bit rl, bits<3> funct3,
@@ -342,7 +338,7 @@ class RVInstRAtomic<bits<5> funct5, bit aq, bit rl, bits<3> funct3,
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = rd;
- let Opcode = opcode.Value;
+ let Inst{6-0} = opcode.Value;
}
class RVInstRFrm<bits<7> funct7, RISCVOpcode opcode, dag outs, dag ins,
@@ -358,7 +354,7 @@ class RVInstRFrm<bits<7> funct7, RISCVOpcode opcode, dag outs, dag ins,
let Inst{19-15} = rs1;
let Inst{14-12} = frm;
let Inst{11-7} = rd;
- let Opcode = opcode.Value;
+ let Inst{6-0} = opcode.Value;
}
class RVInstI<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
@@ -372,7 +368,7 @@ class RVInstI<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = rd;
- let Opcode = opcode.Value;
+ let Inst{6-0} = opcode.Value;
}
class RVInstIShift<bits<5> imm11_7, bits<3> funct3, RISCVOpcode opcode,
@@ -388,7 +384,7 @@ class RVInstIShift<bits<5> imm11_7, bits<3> funct3, RISCVOpcode opcode,
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = rd;
- let Opcode = opcode.Value;
+ let Inst{6-0} = opcode.Value;
}
class RVInstIShiftW<bits<7> imm11_5, bits<3> funct3, RISCVOpcode opcode,
@@ -403,7 +399,7 @@ class RVInstIShiftW<bits<7> imm11_5, bits<3> funct3, RISCVOpcode opcode,
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = rd;
- let Opcode = opcode.Value;
+ let Inst{6-0} = opcode.Value;
}
class RVInstS<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
@@ -418,7 +414,7 @@ class RVInstS<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = imm12{4-0};
- let Opcode = opcode.Value;
+ let Inst{6-0} = opcode.Value;
}
class RVInstB<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
@@ -435,7 +431,7 @@ class RVInstB<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
let Inst{14-12} = funct3;
let Inst{11-8} = imm12{3-0};
let Inst{7} = imm12{10};
- let Opcode = opcode.Value;
+ let Inst{6-0} = opcode.Value;
}
class RVInstU<RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
@@ -446,7 +442,7 @@ class RVInstU<RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
let Inst{31-12} = imm20;
let Inst{11-7} = rd;
- let Opcode = opcode.Value;
+ let Inst{6-0} = opcode.Value;
}
class RVInstJ<RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
@@ -460,7 +456,7 @@ class RVInstJ<RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
let Inst{20} = imm20{10};
let Inst{19-12} = imm20{18-11};
let Inst{11-7} = rd;
- let Opcode = opcode.Value;
+ let Inst{6-0} = opcode.Value;
}
//===----------------------------------------------------------------------===//
@@ -482,7 +478,7 @@ class DirectiveInsnR<dag outs, dag ins, string argstr>
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = rd;
- let Opcode = opcode;
+ let Inst{6-0} = opcode;
let AsmString = ".insn r " # argstr;
}
@@ -504,7 +500,7 @@ class DirectiveInsnR4<dag outs, dag ins, string argstr>
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = rd;
- let Opcode = opcode;
+ let Inst{6-0} = opcode;
let AsmString = ".insn r4 " # argstr;
}
@@ -522,7 +518,7 @@ class DirectiveInsnI<dag outs, dag ins, string argstr>
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = rd;
- let Opcode = opcode;
+ let Inst{6-0} = opcode;
let AsmString = ".insn i " # argstr;
}
@@ -541,7 +537,7 @@ class DirectiveInsnS<dag outs, dag ins, string argstr>
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = imm12{4-0};
- let Opcode = opcode;
+ let Inst{6-0} = opcode;
let AsmString = ".insn s " # argstr;
}
@@ -562,7 +558,7 @@ class DirectiveInsnB<dag outs, dag ins, string argstr>
let Inst{14-12} = funct3;
let Inst{11-8} = imm12{3-0};
let Inst{7} = imm12{10};
- let Opcode = opcode;
+ let Inst{6-0} = opcode;
let AsmString = ".insn b " # argstr;
}
@@ -576,7 +572,7 @@ class DirectiveInsnU<dag outs, dag ins, string argstr>
let Inst{31-12} = imm20;
let Inst{11-7} = rd;
- let Opcode = opcode;
+ let Inst{6-0} = opcode;
let AsmString = ".insn u " # argstr;
}
@@ -590,7 +586,7 @@ class DirectiveInsnJ<dag outs, dag ins, string argstr>
let Inst{31-12} = imm20;
let Inst{11-7} = rd;
- let Opcode = opcode;
+ let Inst{6-0} = opcode;
let AsmString = ".insn j " # argstr;
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td b/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
index 1a234095d23645..6f27c98dd61830 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
@@ -66,7 +66,7 @@ class RVInstSetiVLi<dag outs, dag ins, string opcodestr, string argstr>
let Inst{19-15} = uimm;
let Inst{14-12} = OPCFG.Value;
let Inst{11-7} = rd;
- let Opcode = OPC_OP_V.Value;
+ let Inst{6-0} = OPC_OP_V.Value;
let Defs = [VTYPE, VL];
}
@@ -82,7 +82,7 @@ class RVInstSetVLi<dag outs, dag ins, string opcodestr, string argstr>
let Inst{19-15} = rs1;
let Inst{14-12} = OPCFG.Value;
let Inst{11-7} = rd;
- let Opcode = OPC_OP_V.Value;
+ let Inst{6-0} = OPC_OP_V.Value;
let Defs = [VTYPE, VL];
}
@@ -99,7 +99,7 @@ class RVInstSetVL<dag outs, dag ins, string opcodestr, string argstr>
let Inst{19-15} = rs1;
let Inst{14-12} = OPCFG.Value;
let Inst{11-7} = rd;
- let Opcode = OPC_OP_V.Value;
+ let Inst{6-0} = OPC_OP_V.Value;
let Defs = [VTYPE, VL];
}
@@ -118,7 +118,7 @@ class RVInstVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
let Inst{19-15} = vs1;
let Inst{14-12} = opv.Value;
let Inst{11-7} = vd;
- let Opcode = OPC_OP_V.Value;
+ let Inst{6-0} = OPC_OP_V.Value;
let Uses = [VTYPE, VL];
let RVVConstraint = VMConstraint;
@@ -138,7 +138,7 @@ class RVInstVX<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
let Inst{19-15} = rs1;
let Inst{14-12} = opv.Value;
let Inst{11-7} = vd;
- let Opcode = OPC_OP_V.Value;
+ let Inst{6-0} = OPC_OP_V.Value;
let Uses = [VTYPE, VL];
let RVVConstraint = VMConstraint;
@@ -157,7 +157,7 @@ class RVInstV2<bits<6> funct6, bits<5> vs2, RISCVVFormat opv, dag outs, dag ins,
let Inst{19-15} = rs1;
let Inst{14-12} = opv.Value;
let Inst{11-7} = vd;
- let Opcode = OPC_OP_V.Value;
+ let Inst{6-0} = OPC_OP_V.Value;
let Uses = [VTYPE, VL];
let RVVConstraint = VMConstraint;
@@ -177,7 +177,7 @@ class RVInstIVI<bits<6> funct6, dag outs, dag ins, string opcodestr,
let Inst{19-15} = imm;
let Inst{14-12} = OPIVI.Value;
let Inst{11-7} = vd;
- let Opcode = OPC_OP_V.Value;
+ let Inst{6-0} = OPC_OP_V.Value;
let Uses = [VTYPE, VL];
let RVVConstraint = VMConstraint;
@@ -196,7 +196,7 @@ class RVInstV<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, dag outs,
let Inst{19-15} = vs1;
let Inst{14-12} = opv.Value;
let Inst{11-7} = vd;
- let Opcode = OPC_OP_V.Value;
+ let Inst{6-0} = OPC_OP_V.Value;
let Uses = [VTYPE, VL];
let RVVConstraint = VMConstraint;
@@ -218,7 +218,7 @@ class RVInstVLU<bits<3> nf, bit mew, RISCVLSUMOP lumop,
let Inst{19-15} = rs1;
let Inst{14-12} = width;
let Inst{11-7} = vd;
- let Opcode = OPC_LOAD_FP.Value;
+ let Inst{6-0} = OPC_LOAD_FP.Value;
let Uses = [VTYPE, VL];
let RVVConstraint = VMConstraint;
@@ -240,7 +240,7 @@ class RVInstVLS<bits<3> nf, bit mew, bits<3> width,
let Inst{19-15} = rs1;
let Inst{14-12} = width;
let Inst{11-7} = vd;
- let Opcode = OPC_LOAD_FP.Value;
+ let Inst{6-0} = OPC_LOAD_FP.Value;
let Uses = [VTYPE, VL];
let RVVConstraint = VMConstraint;
@@ -262,7 +262,7 @@ class RVInstVLX<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
let Inst{19-15} = rs1;
let Inst{14-12} = width;
let Inst{11-7} = vd;
- let Opcode = OPC_LOAD_FP.Value;
+ let Inst{6-0} = OPC_LOAD_FP.Value;
let Uses = [VTYPE, VL];
let RVVConstraint = VMConstraint;
@@ -284,7 +284,7 @@ class RVInstVSU<bits<3> nf, bit mew, RISCVLSUMOP sumop,
let Inst{19-15} = rs1;
let Inst{14-12} = width;
let Inst{11-7} = vs3;
- let Opcode = OPC_STORE_FP.Value;
+ let Inst{6-0} = OPC_STORE_FP.Value;
let Uses = [VTYPE, VL];
}
@@ -305,7 +305,7 @@ class RVInstVSS<bits<3> nf, bit mew, bits<3> width,
let Inst{19-15} = rs1;
let Inst{14-12} = width;
let Inst{11-7} = vs3;
- let Opcode = OPC_STORE_FP.Value;
+ let Inst{6-0} = OPC_STORE_FP.Value;
let Uses = [VTYPE, VL];
}
@@ -326,7 +326,7 @@ class RVInstVSX<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
let Inst{19-15} = rs1;
let Inst{14-12} = width;
let Inst{11-7} = vs3;
- let Opcode = OPC_STORE_FP.Value;
+ let Inst{6-0} = OPC_STORE_FP.Value;
let Uses = [VTYPE, VL];
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
index 493eff3a513925..4ba052b25e4283 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
@@ -79,7 +79,7 @@ class CVInstMac<bits<7> funct7, bits<3> funct3, dag outs, dag ins,
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = rd;
- let Opcode = OPC_CUSTOM_1.Value;
+ let Inst{6-0} = OPC_CUSTOM_1.Value;
let DecoderNamespace = "XCVmac";
}
@@ -97,7 +97,7 @@ class CVInstMac16I<bits<2> funct2, bits<3> funct3, dag outs, dag ins,
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = rd;
- let Opcode = OPC_CUSTOM_2.Value;
+ let Inst{6-0} = OPC_CUSTOM_2.Value;
let DecoderNamespace = "XCVmac";
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
index b29bc3d9b0a88b..03ed501ba6a316 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
@@ -82,7 +82,7 @@ class RVInstVCCustom2<bits<4> funct6_hi4, bits<3> funct3, dag outs, dag ins,
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = rd;
- let Opcode = OPC_CUSTOM_2.Value;
+ let Inst{6-0} = OPC_CUSTOM_2.Value;
let Uses = [VTYPE, VL];
let RVVConstraint = NoConstraint;
@@ -105,7 +105,7 @@ class RVInstVCFCustom2<bits<4> funct6_hi4, bits<3> funct3, dag outs, dag ins,
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = rd;
- let Opcode = OPC_CUSTOM_2.Value;
+ let Inst{6-0} = OPC_CUSTOM_2.Value;
let Uses = [VTYPE, VL];
let RVVConstraint = NoConstraint;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
index 58e64e4aec9f9d..e840dfddd8d9bb 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
@@ -37,7 +37,7 @@ class THInstVdotVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
string opcodestr, string argstr>
: RVInstVV<funct6, opv, outs, ins, opcodestr, argstr> {
let Inst{26} = 0;
- let Opcode = OPC_CUSTOM_0.Value;
+ let Inst{6-0} = OPC_CUSTOM_0.Value;
let DecoderNamespace = "THeadV";
}
@@ -45,7 +45,7 @@ class THInstVdotVX<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
string opcodestr, string argstr>
: RVInstVX<funct6, opv, outs, ins, opcodestr, argstr> {
let Inst{26} = 1;
- let Opcode = OPC_CUSTOM_0.Value;
+ let Inst{6-0} = OPC_CUSTOM_0.Value;
let DecoderNamespace = "THeadV";
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
index 977178d99e0fc9..9b81ebe6717f40 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
@@ -65,7 +65,7 @@ class FPUnaryOp_imm<bits<7> funct7, bits<5> rs2val, bits<3> funct3, RISCVOpcode
let Inst{19-15} = imm;
let Inst{14-12} = funct3;
let Inst{11-7} = rd;
- let Opcode = opcode.Value;
+ let Inst{6-0} = opcode.Value;
}
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index 920c16c7dbc6be..98877bb24cc95b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -36,7 +36,7 @@ class RVInstIVI_VROR<bits<6> funct6, dag outs, dag ins, string opcodestr,
let Inst{19-15} = imm{4-0};
let Inst{14-12} = OPIVI.Value;
let Inst{11-7} = vd;
- let Opcode = OPC_OP_V.Value;
+ let Inst{6-0} = OPC_OP_V.Value;
let Uses = [VTYPE, VL];
let RVVConstraint = VMConstraint;
@@ -54,20 +54,20 @@ multiclass VROR_IV_V_X_I<string opcodestr, bits<6> funct6>
// op vd, vs2, vs1
class PALUVVNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr>
: VALUVVNoVm<funct6, opv, opcodestr> {
- let Opcode = OPC_OP_P.Value;
+ let Inst{6-0} = OPC_OP_P.Value;
}
// op vd, vs2, imm, vm
class PALUVINoVm<bits<6> funct6, string opcodestr, Operand optype = simm5>
: VALUVINoVm<funct6, opcodestr, optype> {
- let Opcode = OPC_OP_P.Value;
+ let Inst{6-0} = OPC_OP_P.Value;
let Inst{14-12} = OPMVV.Value;
}
// op vd, vs2 (use vs1 as instruction encoding)
class PALUVs2NoVm<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr>
: VALUVs2NoVm<funct6, vs1, opv, opcodestr> {
- let Opcode = OPC_OP_P.Value;
+ let Inst{6-0} = OPC_OP_P.Value;
}
multiclass VAES_MV_V_S<bits<6> funct6_vv, bits<6> funct6_vs, bits<5> vs1,
@@ -80,7 +80,7 @@ multiclass VAES_MV_V_S<bits<6> funct6_vv, bits<6> funct6_vs, bits<5> vs1,
// to customize one for them.
class VAESKF_MV_I<bits<6> funct6, string opcodestr, Operand optype>
: VALUVINoVm<funct6, opcodestr, optype> {
- let Opcode = OPC_OP_P.Value;
+ let Inst{6-0} = OPC_OP_P.Value;
let Inst{14-12} = OPMVV.Value;
}
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
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