[PATCH] D155551: [PoC][RISCV] Use scalar register for fixed-length vectors

[Wang Pengcheng via Phabricator via llvm-commits]

wangpc added a comment.

In D155551#4517444 <https://reviews.llvm.org/D155551#4517444>, @zixuan-wu wrote:

> Does this optimization only happen in load and store sequence to do memcpy or memset, or something like?
>
> If so, enabling the vectorization in middle end and vector type legal in backend may too aggressive and complicated, because no operations are legal in such types.  Introducing vectorization and backend support for such condition can work, but it influences too much such as evaluation of cost model and other opt as such types are recognized as legal type. Instead, recognizing this condition as memcpy would make sense more.

Yes, it's limited. And we know that RVP is also not suitable for vectorization. I just post this PoC here to gather some feedbacks. :-)
But I think this kind of vectorization is feasible for XCVsimd extension (D153721 <https://reviews.llvm.org/D153721>).


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