[PATCH] D155299: [AArch64][SVE2] Combine add+lsr to rshrnb for stores

[Matt Devereau via Phabricator via llvm-commits]

MattDevereau updated this revision to Diff 542087.
MattDevereau added a comment.

@kmclaughlin Thank you. I've added two tests `@neg_trunc_lsr_add_op1_not_splat` and `@neg_trunc_lsr_op1_not_splat` to bail out of emitting rshrnb when the RHS operands are not splat values.

I've also added a test `@neg_add_has_two_uses` and a check that the add does not have more than one use. Without this it is possible to generate this regression which costs 2 extra cycles

  neg_add_two_use:
    ptrue p0.h
    ld1h { z0.h }, p0/z, [x0]
    rshrnb z1.b, z0.h, #6
    add z0.h, z0.h, #32 // =0x20
    add z0.h, z0.h, z0.h
    st1h { z0.h }, p0, [x2, x3, lsl #1]
    st1b { z1.h }, p0, [x1, x3]
    ret


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155299/new/

https://reviews.llvm.org/D155299

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve2-intrinsics-combine-rshrnb.ll

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