[PATCH] D155299: [AArch64][SVE2] Combine add+lsr to rshrnb for stores
Kerry McLaughlin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 18 07:17:21 PDT 2023
kmclaughlin added inline comments.
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:20103
+ return SDValue();
+ auto AddOp1 = dyn_cast<ConstantSDNode>(DAG.getSplatValue(Add->getOperand(1)));
+ if (!AddOp1)
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Hi @MattDevereau,
You might need to check the value returned by `DAG.getSplatValue` here as I think if the operand is not a splat as expected, the dyn_cast will fail.
Please can you add a negative test for this scenario as well?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D155299/new/
https://reviews.llvm.org/D155299
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