[PATCH] D154933: [PowerPC] Implement llvm.set.rounding intrinsic

[Qiu Chaofan via Phabricator via llvm-commits]

qiucf added a comment.

In D154933#4488776 <https://reviews.llvm.org/D154933#4488776>, @nemanjai wrote:

> What is the plan for handling `nearest, away` rounding mode for which the PPC FPSCR does not have a setting?

According to other arch's implementation, if input is constant, do assert when the mode is unsupported; if it's variable, only handle the lower 2-bits.



================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:8875
+  } else {
+    // In 32-bit mode, store f64, load and update the lower half.
+    int SSFI = MF.getFrameInfo().CreateStackObject(8, Align(8), false);
----------------
nemanjai wrote:
> Is this whole complicated sequence actually better than just expanding this into a library call?
The glibc `fesetround` routine writes as:

```
if (mode > 2) {
  mtfsb1(30);
  if (mode == 3) mtfsb1(31); else mtfsb0(31);
} else {
  mtfsb0(30);
  if (mode == 1) mtfsb1(31); else mtfsb0(31);
}
```

This indeed looks better. But it seems it's not convenient to generate multiple branches in DAG legalization, also for a library call not recorded.

I think such intrinsic should not have any assumption on runtime library (since `fesetround` is included in libc, not compiler-rt).


Repository:
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https://reviews.llvm.org/D154933