[PATCH] D155626: [DAG][AArch64] Fix truncated vscale constant types

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:5754
     if (OpOpcode == ISD::VSCALE && !NewNodesMustHaveLegalTypes)
-      return getVScale(DL, VT, N1.getConstantOperandAPInt(0));
+      return getVScale(
+          DL, VT,
----------------
`SelectionDAG::getVScale` does the right thing by truncating the APInt value, but it only does so after the assert:

  assert(MulImm.getSignificantBits() <= VT.getSizeInBits() &&
            "Immediate does not fit VT");

which fails because for `MulImm=1`, `MulImm.getSignificantBits() ` results in `2`. This happens because it adds the sign bit, which for a 1-bit value is nonsensical. I think the better thing to do is to fix the assert itself.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155626/new/

https://reviews.llvm.org/D155626