[PATCH] D155626: [DAG][AArch64] Fix truncated vscale constant types
Dave Green via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 18 13:18:12 PDT 2023
dmgreen updated this revision to Diff 541699.
dmgreen added a comment.
Just trunc the constant, as opposed to being opinionated about the sign.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D155626/new/
https://reviews.llvm.org/D155626
Files:
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/test/CodeGen/AArch64/sve-vscale.ll
Index: llvm/test/CodeGen/AArch64/sve-vscale.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-vscale.ll
+++ llvm/test/CodeGen/AArch64/sve-vscale.ll
@@ -101,6 +101,17 @@
ret i32 %1
}
+define i1 @rdvl_i1() {
+; CHECK-LABEL: rdvl_i1:
+; CHECK: rdvl x8, #-1
+; CHECK-NEXT: asr x8, x8, #4
+; CHECK-NEXT: and w0, w8, #0x1
+; CHECK-NEXT: ret
+ %a = tail call i64 @llvm.vscale.i64()
+ %b = trunc i64 %a to i1
+ ret i1 %b
+}
+
;
; CNTH
;
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5751,7 +5751,9 @@
if (OpOpcode == ISD::UNDEF)
return getUNDEF(VT);
if (OpOpcode == ISD::VSCALE && !NewNodesMustHaveLegalTypes)
- return getVScale(DL, VT, N1.getConstantOperandAPInt(0));
+ return getVScale(
+ DL, VT,
+ N1.getConstantOperandAPInt(0).trunc(VT.getScalarSizeInBits()));
break;
case ISD::ANY_EXTEND_VECTOR_INREG:
case ISD::ZERO_EXTEND_VECTOR_INREG:
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