[PATCH] D155592: [AArch64] Reuse larger DUPLANE if available

Tue Jul 18 08:55:27 PDT 2023

jaykang10 added inline comments.

================
Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:6950
 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull", AArch64smull>;
+def : Pat<(v4i32 (AArch64smull (v4i16 V64:$Rn),
+                        (extract_low_dup_v8i16 (v8i16 V128:$Rm), VectorIndexS:$idx))),
----------------
jaykang10 wrote:
> dmgreen wrote:
> > Would this be needed for all the "AdvSIMD indexed element" operations?
> > 
> > Is there some way to make that fairly generic? Maybe a PatFrag that matches either `v4i16 (AArch64duplane16(..` or `extract_subvector (AArch64duplane16 (..`, that can be used in the instruction patterns like those in SIMDVectorIndexedHSTied.
> I was not just sure the patterns are needed for all `SIMD indexed` operations.
> If it is ok, let me move the patterns into `SIMDIndexedLongSD`.
Additionally, when I added `def v2i32_indexed_low` in `SIMDVectorIndexedLongSD`, I got Decoding conflict as below because it causes same encoding so I added `Pat`s.
```
Decoding Conflict:
		0000111110......1010.0..........
		0000111110......1010............
		0000111110......................
		...0111110......................
		...011..........................
		................................
	SMULLv2i32_indexed 0000111110______1010_0__________
	SMULLv2i32_indexed_low 0000111110______1010_0__________
Decoding Conflict:
		0010111110......1010.0..........
		0010111110......1010............
		0010111110......................
		...0111110......................
		...011..........................
		................................
	UMULLv2i32_indexed 0010111110______1010_0__________
	UMULLv2i32_indexed_low 0010111110______1010_0__________
```

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155592/new/

https://reviews.llvm.org/D155592