[PATCH] D155592: [AArch64] Reuse larger DUPLANE if available

Tue Jul 18 08:27:50 PDT 2023

jaykang10 added inline comments.

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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:22119

   return performPostLD1Combine(N, DCI, false);
 }
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dmgreen wrote:
> Should this be excluded for everything that isn't DUP?
I do not know how the `performPostLD1Combine` function works in detail but the function checks whether the input node is `ISD::LOAD`. If it is not `ISD::LOAD`, the function returns `SDValue()`.
To be safe, let me update code which do not execute the `performPostLD1Combine` function with DUPLANE.

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Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:6950
 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull", AArch64smull>;
+def : Pat<(v4i32 (AArch64smull (v4i16 V64:$Rn),
+                        (extract_low_dup_v8i16 (v8i16 V128:$Rm), VectorIndexS:$idx))),
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dmgreen wrote:
> Would this be needed for all the "AdvSIMD indexed element" operations?
> 
> Is there some way to make that fairly generic? Maybe a PatFrag that matches either `v4i16 (AArch64duplane16(..` or `extract_subvector (AArch64duplane16 (..`, that can be used in the instruction patterns like those in SIMDVectorIndexedHSTied.
I was not just sure the patterns are needed for all `SIMD indexed` operations.
If it is ok, let me move the patterns into `SIMDIndexedLongSD`.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155592/new/

https://reviews.llvm.org/D155592