[PATCH] D155551: [PoC][RISCV] Use scalar register for fixed-length vectors

[Wang Pengcheng via Phabricator via llvm-commits]

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So that we can vectorize some loops with small element size.

For small vectors like v4i8, v8i8, v4i16, etc., they can be fit in
a whole scalar register.

I don't know if this is the right way to go and no other target
has done something like this. The changes seem to be intrusive, and
we have a lot of works to do if we want go further.

Related discussion:

- https://discourse.llvm.org/t/freertos-queue-much-slower-on-riscv-when-compiled-with-llvm-rather-than-gcc


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D155551

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
  llvm/test/CodeGen/RISCV/vectorization-scalar-register/memcpy.ll

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