[PATCH] D138809: [RISCV] Support vector crypto extension LLVM IR

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:7339
+  defm : VPatUnaryV_V<"int_riscv_vcpopv", "PseudoVCPOP", AllIntegerVectors>;
+  defm : VPatBinaryV_VV_VX<"int_riscv_vrol", "PseudoVROL", AllIntegerVectors>;
+  defm : VPatBinaryV_VV_VX_VI<"int_riscv_vror", "PseudoVROR", AllIntegerVectors>;
----------------
We will need to implement a VI version of the vrol intrinsic using the vror.vi instruction by changing the amount to sew-rotamount.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:7340
+  defm : VPatBinaryV_VV_VX<"int_riscv_vrol", "PseudoVROL", AllIntegerVectors>;
+  defm : VPatBinaryV_VV_VX_VI<"int_riscv_vror", "PseudoVROR", AllIntegerVectors>;
+  defm : VPatBinaryW_VV_VX_VI<"int_riscv_vwsll", "PseudoVWSLL", AllWidenableIntVectors>;
----------------
VPatBinaryV_VV_VX_VI defaults simm5, but vror.vi uses uimm6.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138809/new/

https://reviews.llvm.org/D138809