[PATCH] D155439: [RISCV] Add SDNode patterns for vrol.[vv,vx] and vror.[vv,vx,vi]
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 17 12:42:40 PDT 2023
craig.topper added inline comments.
================
Comment at: llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll:85
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-ZVBB-NEXT: vror.vi v8, v8, -1
+; CHECK-ZVBB-NEXT: ret
----------------
I suspect the assembler won't parse this.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D155439/new/
https://reviews.llvm.org/D155439
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