[PATCH] D155439: [RISCV] Add SDNode patterns for vrol.[vv,vx] and vror.[vv,vx,vi]

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:3006
 
-bool RISCVDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &SplatVal) {
+template <unsigned Bits>
+constexpr inline bool selectVSplatUimm(SDValue N, SDValue &SplatVal,
----------------
craig.topper wrote:
> craig.topper wrote:
> > Don't template this, pass the value as an argument. There show be a form of `isUInt` that takes an argument.
> "show" was supposed to be "should"
You can make a remplate version of `selectVSplatUimm` that takes a template parameter and forwards the argument as a non-template parameter. 

See for example

```
  bool selectSExtBits(SDValue N, unsigned Bits, SDValue &Val);                   
  template <unsigned Bits> bool selectSExtBits(SDValue N, SDValue &Val) {        
    return selectSExtBits(N, Bits, Val);                                         
  }   
```

Basically I'm trying to avoid the binary bloat from duplicating a function that barely cares about the number of bits.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D155439/new/

https://reviews.llvm.org/D155439