[PATCH] D155418: [RISCV] Add bf16 as a valid type for the FPR16 register class.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Jul 16 23:07:50 PDT 2023
craig.topper added a comment.
In D155418#4504766 <https://reviews.llvm.org/D155418#4504766>, @joshua-arch1 wrote:
> In D155418#4504763 <https://reviews.llvm.org/D155418#4504763>, @craig.topper wrote:
>
>> In D155418#4504759 <https://reviews.llvm.org/D155418#4504759>, @joshua-arch1 wrote:
>>
>>> Why are some patterns using FPR32 and FPR64 modified too?
>>
>> Because they use the same classes in tablegen and I had to add a `ValueType` parameter to them.
>
> I suppose that will be hard to maintain. Can we custom codegen classes for f16/bf16 in tablegen?
Can you explain why it will be hard to maintain? The complexity of supporting Zfinx/Zdinx/Zhinx and all the special patterns for Zfhmin already seems way worse than passing an extra Valuetype to some classes.
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https://reviews.llvm.org/D155418/new/
https://reviews.llvm.org/D155418
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