[PATCH] D154756: [AArch64] Add scheduling model for Neoverse V1

[Evandro Menezes via Phabricator via llvm-commits]

evandro marked an inline comment as done.
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Comment at: llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td:950
 def V2Wr_IMA  : SchedWriteRes<[V2UnitM0]> { let Latency = 2; }
 def V2Wr_IMUL : SchedWriteVariant<[
+                  SchedVar<NeoverseMULIdiomPred, [V2Wr_IM]>,
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dmgreen wrote:
> This is only used in regexes, so likely doesn't need to change. Is NeoverseMULIdiomPred being added because the V1 uses WriteIM64 and that is used for mulhi too? They both have overrides for SMULHrr/UMULHrr, so I'm not sure this will do anything over using IsReg3ZeroPred directly.
> 
> Otherwise it looks like IsReg3ZeroPred is now unused, if you did have a reason to stick with NeoverseMULIdiomPred.
In V1, multiply high has its own `SchedWriteRes`.  `NeoverseMULIdiomPred` does use the predicate `CheckIsReg3Zero`, on which `IsReg3ZeroPred` is based on.


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  https://reviews.llvm.org/D154756/new/

https://reviews.llvm.org/D154756