[PATCH] D154756: [AArch64] Add scheduling model for Neoverse V1

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td:950
 def V2Wr_IMA  : SchedWriteRes<[V2UnitM0]> { let Latency = 2; }
 def V2Wr_IMUL : SchedWriteVariant<[
+                  SchedVar<NeoverseMULIdiomPred, [V2Wr_IM]>,
----------------
This is only used in regexes, so likely doesn't need to change. Is NeoverseMULIdiomPred being added because the V1 uses WriteIM64 and that is used for mulhi too? They both have overrides for SMULHrr/UMULHrr, so I'm not sure this will do anything over using IsReg3ZeroPred directly.

Otherwise it looks like IsReg3ZeroPred is now unused, if you did have a reason to stick with NeoverseMULIdiomPred.


================
Comment at: llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-neon-instructions.s:22
+addp v0.8b, v0.8b, v0.8b
+and v0.8b, v0.8b, v0.8b
+bic v0.4h, #15, lsl #8
----------------
evandro wrote:
> dmgreen wrote:
> > evandro wrote:
> > > dmgreen wrote:
> > > > The Neoverse-V2 version of this file has some extra instructions like addv's, aes and some dup instructions, among others.
> > > It has many more instructions, but SVE2 ones.  I'll add more coverage here.
> > Thanks - And what about the extra Neon instructions?
> There were only a handfull of Neon instructions missing that were added here.
I still see differences between
```
diff llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-neon-instructions.s llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s
```
It would be good to make sure that we are not missing coverage of some of the neon instructions.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154756/new/

https://reviews.llvm.org/D154756