[PATCH] D155150: [RISCV] Lower VP_CTLZ_ZERO_UNDEF/VP_CTTZ_ZERO_UNDEF/VP_CTLZ by converting to FP and extracting the exponent.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4319
   if (FloatVT.bitsGT(VT)) {
     FloatVal = DAG.getNode(ISD::UINT_TO_FP, DL, FloatVT, Src);
+    if (Op->isVPOpcode())
----------------
We should skip creating the non-VP node this node if it's a VPOpcode


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4349
+    // Restore back to original type. Truncation after SRL is to generate vnsrl.
+    if (IntVT.bitsLT(VT))
+      Exp = DAG.getNode(ISD::VP_ZERO_EXTEND, DL, VT, Exp, Mask, VL);
----------------
Can we use DAG.getVPZExtOrTrunc


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4374
   unsigned Adjust = ExponentBias + (EltSize - 1);
   SDValue Res =
       DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(Adjust, DL, VT), Exp);
----------------
Don't create this new if its a VP opcode


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155150/new/

https://reviews.llvm.org/D155150