[PATCH] D144829: [WIP][BPF] Add a few new insns under cpu=v4

Alexei Starovoitov via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Jul 14 08:49:57 PDT 2023


ast added inline comments.


================
Comment at: llvm/lib/Target/BPF/BPFInstrInfo.td:56
 def BPFNoALU32 : Predicate<"!Subtarget->getHasAlu32()">;
+def BPFHasCPUv4_ldsx : Predicate<"Subtarget->getCPUv4_ldsx()">;
+def BPFHasCPUv4_movsx : Predicate<"Subtarget->getCPUv4_movsx()">;
----------------
Here and elsewhere... let's drop CPUv4 mid prefix. imo the extra verbosity doesn't improve readability.
Same with the flag: disable-cpuv4-movsx. I can be disable-movsx.

s/BPFHasCPUv4_ldsx/BPFHasLdsx/
s/getCPUv4_bswap/getHasBswap/ or even shorter hasBswap ?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144829/new/

https://reviews.llvm.org/D144829



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