[PATCH] D155299: [AArch64][SVE2] Combine add+lsr to rshrnb for stores

[Matt Devereau via Phabricator via llvm-commits]

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[AArch64][SVE2] Combine add+lsr to rshrnb for stores

With the sequence

  add z0.h, z0.h, 1 << shiftimm
  lsr z0.h, shiftimm
  st1b z0.h, x1

This can be replaced with

  rshrnb z0.b, shiftimm
  st1b z0.h, x1

When we know the top half of the destination register is ignored by the store.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D155299

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve2-intrinsics-binary-narrowing-shr.ll
  llvm/test/CodeGen/AArch64/sve2-intrinsics-combine-rshrnb.ll

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