[llvm] b159c5f - [SystemZ] Use named MI sub-operands
Ilya Leoshkevich via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 14 08:05:28 PDT 2023
Author: Ilya Leoshkevich
Date: 2023-07-14T17:05:19+02:00
New Revision: b159c5f958f747308987b4d48a2070c9394d3450
URL: https://github.com/llvm/llvm-project/commit/b159c5f958f747308987b4d48a2070c9394d3450
DIFF: https://github.com/llvm/llvm-project/commit/b159c5f958f747308987b4d48a2070c9394d3450.diff
LOG: [SystemZ] Use named MI sub-operands
Prepare for removing the MemOpsEmitted workaround for symbolic
displacements by letting TableGen know about the offsets of the
displacement sub-operands within the instruction.
There are alternative ways to do this that were tried and rejected:
- Creating encoders and decoders for each possible displacement offset.
This is too repetitive.
- Use VarLenCodeEmitter [1]. The resulting diff is quite large.
Instead, use the named sub-operand support introduced by commit
a538d1f13a13 ("[TableGen][CodeEmitterGen] Allow local names for
sub-operands in a operand list.").
Describe instruction encodings in terms of sub-operands instead of
operands (e.g. B, D, L vs BDL) - this also better matches the pictures
from the Principles of Operation. Decompose operands into sub-operands
using the new (bdaddr12only $B1, $D1):$BD1 syntax. Replace the
encoders and the decoders of the operands with these of the
sub-operands.
Since DecodeADDR64BitRegisterClass() is now used for bases and indices,
change it to return NoRegister when decoding 0. This also changes the
disassembly of some instructions, e.g., br %r0 becomes br 0. Since this
better captures the instruction semantics, namely, that the value of
%r0 is not used, keep this change and update the tests.
[1] https://m680x0.github.io/blog/2022/02/varlen-encoder.html
Reviewed By: uweigand
Differential Revision: https://reviews.llvm.org/D155194
Added:
Modified:
llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp
llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
llvm/lib/Target/SystemZ/SystemZInstrFormats.td
llvm/lib/Target/SystemZ/SystemZInstrInfo.td
llvm/lib/Target/SystemZ/SystemZInstrVector.td
llvm/lib/Target/SystemZ/SystemZOperands.td
llvm/test/MC/Disassembler/SystemZ/insns-pcrel.txt
llvm/test/MC/Disassembler/SystemZ/insns.txt
Removed:
################################################################################
diff --git a/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp b/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp
index 0c6c1090766328..d26ad63dc515dd 100644
--- a/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp
+++ b/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp
@@ -79,11 +79,16 @@ static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
}
static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
- const unsigned *Regs, unsigned Size) {
+ const unsigned *Regs, unsigned Size,
+ bool IsAddr = false) {
assert(RegNo < Size && "Invalid register");
- RegNo = Regs[RegNo];
- if (RegNo == 0)
- return MCDisassembler::Fail;
+ if (IsAddr && RegNo == 0) {
+ RegNo = SystemZ::NoRegister;
+ } else {
+ RegNo = Regs[RegNo];
+ if (RegNo == 0)
+ return MCDisassembler::Fail;
+ }
Inst.addOperand(MCOperand::createReg(RegNo));
return MCDisassembler::Success;
}
@@ -112,10 +117,16 @@ static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
return decodeRegisterClass(Inst, RegNo, SystemZMC::GR128Regs, 16);
}
+static DecodeStatus
+DecodeADDR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address,
+ const MCDisassembler *Decoder) {
+ return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs, 16, true);
+}
+
static DecodeStatus
DecodeADDR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address,
const MCDisassembler *Decoder) {
- return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16);
+ return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16, true);
}
static DecodeStatus DecodeFP32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
@@ -242,12 +253,28 @@ static DecodeStatus decodeS16ImmOperand(MCInst &Inst, uint64_t Imm,
return decodeSImmOperand<16>(Inst, Imm);
}
+static DecodeStatus decodeS20ImmOperand(MCInst &Inst, uint64_t Imm,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ return decodeSImmOperand<20>(Inst, Imm);
+}
+
static DecodeStatus decodeS32ImmOperand(MCInst &Inst, uint64_t Imm,
uint64_t Address,
const MCDisassembler *Decoder) {
return decodeSImmOperand<32>(Inst, Imm);
}
+template <unsigned N>
+static DecodeStatus decodeLenOperand(MCInst &Inst, uint64_t Imm,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ if (!isUInt<N>(Imm))
+ return MCDisassembler::Fail;
+ Inst.addOperand(MCOperand::createImm(Imm + 1));
+ return MCDisassembler::Success;
+}
+
template <unsigned N>
static DecodeStatus decodePCDBLOperand(MCInst &Inst, uint64_t Imm,
uint64_t Address, bool isBranch,
@@ -292,158 +319,6 @@ static DecodeStatus decodePC32DBLOperand(MCInst &Inst, uint64_t Imm,
return decodePCDBLOperand<32>(Inst, Imm, Address, false, Decoder);
}
-static DecodeStatus decodeBDAddr12Operand(MCInst &Inst, uint64_t Field,
- const unsigned *Regs) {
- uint64_t Base = Field >> 12;
- uint64_t Disp = Field & 0xfff;
- assert(Base < 16 && "Invalid BDAddr12");
- Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
- Inst.addOperand(MCOperand::createImm(Disp));
- return MCDisassembler::Success;
-}
-
-static DecodeStatus decodeBDAddr20Operand(MCInst &Inst, uint64_t Field,
- const unsigned *Regs) {
- uint64_t Base = Field >> 20;
- uint64_t Disp = ((Field << 12) & 0xff000) | ((Field >> 8) & 0xfff);
- assert(Base < 16 && "Invalid BDAddr20");
- Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
- Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp)));
- return MCDisassembler::Success;
-}
-
-static DecodeStatus decodeBDXAddr12Operand(MCInst &Inst, uint64_t Field,
- const unsigned *Regs) {
- uint64_t Index = Field >> 16;
- uint64_t Base = (Field >> 12) & 0xf;
- uint64_t Disp = Field & 0xfff;
- assert(Index < 16 && "Invalid BDXAddr12");
- Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
- Inst.addOperand(MCOperand::createImm(Disp));
- Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index]));
- return MCDisassembler::Success;
-}
-
-static DecodeStatus decodeBDXAddr20Operand(MCInst &Inst, uint64_t Field,
- const unsigned *Regs) {
- uint64_t Index = Field >> 24;
- uint64_t Base = (Field >> 20) & 0xf;
- uint64_t Disp = ((Field & 0xfff00) >> 8) | ((Field & 0xff) << 12);
- assert(Index < 16 && "Invalid BDXAddr20");
- Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
- Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp)));
- Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index]));
- return MCDisassembler::Success;
-}
-
-static DecodeStatus decodeBDLAddr12Len4Operand(MCInst &Inst, uint64_t Field,
- const unsigned *Regs) {
- uint64_t Length = Field >> 16;
- uint64_t Base = (Field >> 12) & 0xf;
- uint64_t Disp = Field & 0xfff;
- assert(Length < 16 && "Invalid BDLAddr12Len4");
- Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
- Inst.addOperand(MCOperand::createImm(Disp));
- Inst.addOperand(MCOperand::createImm(Length + 1));
- return MCDisassembler::Success;
-}
-
-static DecodeStatus decodeBDLAddr12Len8Operand(MCInst &Inst, uint64_t Field,
- const unsigned *Regs) {
- uint64_t Length = Field >> 16;
- uint64_t Base = (Field >> 12) & 0xf;
- uint64_t Disp = Field & 0xfff;
- assert(Length < 256 && "Invalid BDLAddr12Len8");
- Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
- Inst.addOperand(MCOperand::createImm(Disp));
- Inst.addOperand(MCOperand::createImm(Length + 1));
- return MCDisassembler::Success;
-}
-
-static DecodeStatus decodeBDRAddr12Operand(MCInst &Inst, uint64_t Field,
- const unsigned *Regs) {
- uint64_t Length = Field >> 16;
- uint64_t Base = (Field >> 12) & 0xf;
- uint64_t Disp = Field & 0xfff;
- assert(Length < 16 && "Invalid BDRAddr12");
- Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
- Inst.addOperand(MCOperand::createImm(Disp));
- Inst.addOperand(MCOperand::createReg(Regs[Length]));
- return MCDisassembler::Success;
-}
-
-static DecodeStatus decodeBDVAddr12Operand(MCInst &Inst, uint64_t Field,
- const unsigned *Regs) {
- uint64_t Index = Field >> 16;
- uint64_t Base = (Field >> 12) & 0xf;
- uint64_t Disp = Field & 0xfff;
- assert(Index < 32 && "Invalid BDVAddr12");
- Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
- Inst.addOperand(MCOperand::createImm(Disp));
- Inst.addOperand(MCOperand::createReg(SystemZMC::VR128Regs[Index]));
- return MCDisassembler::Success;
-}
-
-static DecodeStatus decodeBDAddr32Disp12Operand(MCInst &Inst, uint64_t Field,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- return decodeBDAddr12Operand(Inst, Field, SystemZMC::GR32Regs);
-}
-
-static DecodeStatus decodeBDAddr32Disp20Operand(MCInst &Inst, uint64_t Field,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- return decodeBDAddr20Operand(Inst, Field, SystemZMC::GR32Regs);
-}
-
-static DecodeStatus decodeBDAddr64Disp12Operand(MCInst &Inst, uint64_t Field,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- return decodeBDAddr12Operand(Inst, Field, SystemZMC::GR64Regs);
-}
-
-static DecodeStatus decodeBDAddr64Disp20Operand(MCInst &Inst, uint64_t Field,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- return decodeBDAddr20Operand(Inst, Field, SystemZMC::GR64Regs);
-}
-
-static DecodeStatus
-decodeBDXAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address,
- const MCDisassembler *Decoder) {
- return decodeBDXAddr12Operand(Inst, Field, SystemZMC::GR64Regs);
-}
-
-static DecodeStatus
-decodeBDXAddr64Disp20Operand(MCInst &Inst, uint64_t Field, uint64_t Address,
- const MCDisassembler *Decoder) {
- return decodeBDXAddr20Operand(Inst, Field, SystemZMC::GR64Regs);
-}
-
-static DecodeStatus
-decodeBDLAddr64Disp12Len4Operand(MCInst &Inst, uint64_t Field, uint64_t Address,
- const MCDisassembler *Decoder) {
- return decodeBDLAddr12Len4Operand(Inst, Field, SystemZMC::GR64Regs);
-}
-
-static DecodeStatus
-decodeBDLAddr64Disp12Len8Operand(MCInst &Inst, uint64_t Field, uint64_t Address,
- const MCDisassembler *Decoder) {
- return decodeBDLAddr12Len8Operand(Inst, Field, SystemZMC::GR64Regs);
-}
-
-static DecodeStatus
-decodeBDRAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address,
- const MCDisassembler *Decoder) {
- return decodeBDRAddr12Operand(Inst, Field, SystemZMC::GR64Regs);
-}
-
-static DecodeStatus
-decodeBDVAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address,
- const MCDisassembler *Decoder) {
- return decodeBDVAddr12Operand(Inst, Field, SystemZMC::GR64Regs);
-}
-
#include "SystemZGenDisassemblerTables.inc"
DecodeStatus SystemZDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
index e14abd78ccffcb..c52fb7d55c06e1 100644
--- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
+++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
@@ -73,30 +73,16 @@ class SystemZMCCodeEmitter : public MCCodeEmitter {
// The index or length, if any, is encoded first, followed by the base,
// followed by the displacement. In a 20-bit displacement,
// the low 12 bits are encoded before the high 8 bits.
- uint64_t getBDAddr12Encoding(const MCInst &MI, unsigned OpNum,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
- uint64_t getBDAddr20Encoding(const MCInst &MI, unsigned OpNum,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
- uint64_t getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
- uint64_t getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
- uint64_t getBDLAddr12Len4Encoding(const MCInst &MI, unsigned OpNum,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
- uint64_t getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
- uint64_t getBDRAddr12Encoding(const MCInst &MI, unsigned OpNum,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
- uint64_t getBDVAddr12Encoding(const MCInst &MI, unsigned OpNum,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
+ template <unsigned N>
+ uint64_t getLenEncoding(const MCInst &MI, unsigned OpNum,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
+ uint64_t getDisp12Encoding(const MCInst &MI, unsigned OpNum,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
+ uint64_t getDisp20Encoding(const MCInst &MI, unsigned OpNum,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
// Operand OpNum of MI needs a PC-relative fixup of kind Kind at
// Offset bytes from the start of MI. Add the fixup to Fixups
@@ -201,91 +187,26 @@ getDispOpValue(const MCInst &MI, unsigned OpNum,
llvm_unreachable("Unexpected operand type!");
}
-uint64_t SystemZMCCodeEmitter::
-getBDAddr12Encoding(const MCInst &MI, unsigned OpNum,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
- uint64_t Disp = getDispOpValue(MI, OpNum + 1, Fixups, SystemZ::FK_390_12);
- assert(isUInt<4>(Base) && isUInt<12>(Disp));
- return (Base << 12) | Disp;
-}
-
-uint64_t SystemZMCCodeEmitter::
-getBDAddr20Encoding(const MCInst &MI, unsigned OpNum,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
- uint64_t Disp = getDispOpValue(MI, OpNum + 1, Fixups, SystemZ::FK_390_20);
- assert(isUInt<4>(Base) && isInt<20>(Disp));
- return (Base << 20) | ((Disp & 0xfff) << 8) | ((Disp & 0xff000) >> 12);
-}
-
-uint64_t SystemZMCCodeEmitter::
-getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
- uint64_t Disp = getDispOpValue(MI, OpNum + 1, Fixups, SystemZ::FK_390_12);
- uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI);
- assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index));
- return (Index << 16) | (Base << 12) | Disp;
-}
-
-uint64_t SystemZMCCodeEmitter::
-getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
- uint64_t Disp = getDispOpValue(MI, OpNum + 1, Fixups, SystemZ::FK_390_20);
- uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI);
- assert(isUInt<4>(Base) && isInt<20>(Disp) && isUInt<4>(Index));
- return (Index << 24) | (Base << 20) | ((Disp & 0xfff) << 8)
- | ((Disp & 0xff000) >> 12);
-}
-
-uint64_t SystemZMCCodeEmitter::
-getBDLAddr12Len4Encoding(const MCInst &MI, unsigned OpNum,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
- uint64_t Disp = getDispOpValue(MI, OpNum + 1, Fixups, SystemZ::FK_390_12);
- uint64_t Len = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI) - 1;
- assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Len));
- return (Len << 16) | (Base << 12) | Disp;
-}
-
-uint64_t SystemZMCCodeEmitter::
-getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
- uint64_t Disp = getDispOpValue(MI, OpNum + 1, Fixups, SystemZ::FK_390_12);
- uint64_t Len = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI) - 1;
- assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<8>(Len));
- return (Len << 16) | (Base << 12) | Disp;
+template <unsigned N>
+uint64_t
+SystemZMCCodeEmitter::getLenEncoding(const MCInst &MI, unsigned OpNum,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ return getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI) - 1;
}
-uint64_t SystemZMCCodeEmitter::
-getBDRAddr12Encoding(const MCInst &MI, unsigned OpNum,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
- uint64_t Disp = getDispOpValue(MI, OpNum + 1, Fixups, SystemZ::FK_390_12);
- uint64_t Len = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI);
- assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Len));
- return (Len << 16) | (Base << 12) | Disp;
+uint64_t
+SystemZMCCodeEmitter::getDisp12Encoding(const MCInst &MI, unsigned OpNum,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ return getDispOpValue(MI, OpNum, Fixups, SystemZ::FixupKind::FK_390_12);
}
-uint64_t SystemZMCCodeEmitter::
-getBDVAddr12Encoding(const MCInst &MI, unsigned OpNum,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
- uint64_t Disp = getDispOpValue(MI, OpNum + 1, Fixups, SystemZ::FK_390_12);
- uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI);
- assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<5>(Index));
- return (Index << 16) | (Base << 12) | Disp;
+uint64_t
+SystemZMCCodeEmitter::getDisp20Encoding(const MCInst &MI, unsigned OpNum,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ return getDispOpValue(MI, OpNum, Fixups, SystemZ::FixupKind::FK_390_20);
}
uint64_t
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
index 632dcd8f8a7ec8..a25719f80ad077 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -172,11 +172,9 @@ def getTwoOperandOpcode : InstrMapping {
// bits<4> Rn : register input or output for operand n
// bits<5> Vn : vector register input or output for operand n
// bits<m> In : immediate value of width m for operand n
-// bits<4> BDn : address operand n, which has a base and a displacement
-// bits<m> XBDn : address operand n, which has an index, a base and a
-// displacement
-// bits<m> VBDn : address operand n, which has a vector index, a base and a
-// displacement
+// bits<4> Bn : base register for address operand n
+// bits<m> Dn : displacement for address operand n
+// bits<5> Vn : vector index for address operand n
// bits<4> Xn : index register for address operand n
// bits<4> Mn : mode value for operand n
//
@@ -452,12 +450,14 @@ class InstRIS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<4> R1;
bits<8> I2;
bits<4> M3;
- bits<16> BD4;
+ bits<4> B4;
+ bits<12> D4;
let Inst{47-40} = op{15-8};
let Inst{39-36} = R1;
let Inst{35-32} = M3;
- let Inst{31-16} = BD4;
+ let Inst{31-28} = B4;
+ let Inst{27-16} = D4;
let Inst{15-8} = I2;
let Inst{7-0} = op{7-0};
}
@@ -596,12 +596,14 @@ class InstRRS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<4> R1;
bits<4> R2;
bits<4> M3;
- bits<16> BD4;
+ bits<4> B4;
+ bits<12> D4;
let Inst{47-40} = op{15-8};
let Inst{39-36} = R1;
let Inst{35-32} = R2;
- let Inst{31-16} = BD4;
+ let Inst{31-28} = B4;
+ let Inst{27-16} = D4;
let Inst{15-12} = M3;
let Inst{11-8} = 0;
let Inst{7-0} = op{7-0};
@@ -613,11 +615,15 @@ class InstRXa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
field bits<32> SoftFail = 0;
bits<4> R1;
- bits<20> XBD2;
+ bits<4> X2;
+ bits<4> B2;
+ bits<12> D2;
let Inst{31-24} = op;
let Inst{23-20} = R1;
- let Inst{19-0} = XBD2;
+ let Inst{19-16} = X2;
+ let Inst{15-12} = B2;
+ let Inst{11-0} = D2;
let HasIndex = 1;
}
@@ -628,11 +634,15 @@ class InstRXb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
field bits<32> SoftFail = 0;
bits<4> M1;
- bits<20> XBD2;
+ bits<4> X2;
+ bits<4> B2;
+ bits<12> D2;
let Inst{31-24} = op;
let Inst{23-20} = M1;
- let Inst{19-0} = XBD2;
+ let Inst{19-16} = X2;
+ let Inst{15-12} = B2;
+ let Inst{11-0} = D2;
let HasIndex = 1;
}
@@ -643,12 +653,16 @@ class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
field bits<48> SoftFail = 0;
bits<4> R1;
- bits<20> XBD2;
+ bits<4> X2;
+ bits<4> B2;
+ bits<12> D2;
bits<4> M3;
let Inst{47-40} = op{15-8};
let Inst{39-36} = R1;
- let Inst{35-16} = XBD2;
+ let Inst{35-32} = X2;
+ let Inst{31-28} = B2;
+ let Inst{27-16} = D2;
let Inst{15-12} = M3;
let Inst{11-8} = 0;
let Inst{7-0} = op{7-0};
@@ -663,11 +677,15 @@ class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<4> R1;
bits<4> R3;
- bits<20> XBD2;
+ bits<4> X2;
+ bits<4> B2;
+ bits<12> D2;
let Inst{47-40} = op{15-8};
let Inst{39-36} = R3;
- let Inst{35-16} = XBD2;
+ let Inst{35-32} = X2;
+ let Inst{31-28} = B2;
+ let Inst{27-16} = D2;
let Inst{15-12} = R1;
let Inst{11-8} = 0;
let Inst{7-0} = op{7-0};
@@ -681,11 +699,16 @@ class InstRXYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
field bits<48> SoftFail = 0;
bits<4> R1;
- bits<28> XBD2;
+ bits<4> X2;
+ bits<4> B2;
+ bits<20> D2;
let Inst{47-40} = op{15-8};
let Inst{39-36} = R1;
- let Inst{35-8} = XBD2;
+ let Inst{35-32} = X2;
+ let Inst{31-28} = B2;
+ let Inst{27-16} = D2{11-0};
+ let Inst{15-8} = D2{19-12};
let Inst{7-0} = op{7-0};
let Has20BitOffset = 1;
@@ -698,11 +721,16 @@ class InstRXYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
field bits<48> SoftFail = 0;
bits<4> M1;
- bits<28> XBD2;
+ bits<4> X2;
+ bits<4> B2;
+ bits<20> D2;
let Inst{47-40} = op{15-8};
let Inst{39-36} = M1;
- let Inst{35-8} = XBD2;
+ let Inst{35-32} = X2;
+ let Inst{31-28} = B2;
+ let Inst{27-16} = D2{11-0};
+ let Inst{15-8} = D2{19-12};
let Inst{7-0} = op{7-0};
let Has20BitOffset = 1;
@@ -716,12 +744,14 @@ class InstRSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<4> R1;
bits<4> R3;
- bits<16> BD2;
+ bits<4> B2;
+ bits<12> D2;
let Inst{31-24} = op;
let Inst{23-20} = R1;
let Inst{19-16} = R3;
- let Inst{15-0} = BD2;
+ let Inst{15-12} = B2;
+ let Inst{11-0} = D2;
}
class InstRSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
@@ -731,12 +761,33 @@ class InstRSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<4> R1;
bits<4> M3;
- bits<16> BD2;
+ bits<4> B2;
+ bits<12> D2;
let Inst{31-24} = op;
let Inst{23-20} = R1;
let Inst{19-16} = M3;
- let Inst{15-0} = BD2;
+ let Inst{15-12} = B2;
+ let Inst{11-0} = D2;
+}
+
+class InstRSEa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstSystemZ<6, outs, ins, asmstr, pattern> {
+ field bits<48> Inst;
+ field bits<48> SoftFail = 0;
+
+ bits<4> R1;
+ bits<4> R3;
+ bits<4> B2;
+ bits<12> D2;
+
+ let Inst{47-40} = op{15-8};
+ let Inst{39-36} = R1;
+ let Inst{35-32} = R3;
+ let Inst{31-28} = B2;
+ let Inst{27-16} = D2;
+ let Inst{15-8} = 0;
+ let Inst{7-0} = op{7-0};
}
class InstRSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
@@ -759,12 +810,15 @@ class InstRSLa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
field bits<48> Inst;
field bits<48> SoftFail = 0;
- bits<20> BDL1;
+ bits<4> B1;
+ bits<12> D1;
+ bits<4> L1;
let Inst{47-40} = op{15-8};
- let Inst{39-36} = BDL1{19-16};
+ let Inst{39-36} = L1;
let Inst{35-32} = 0;
- let Inst{31-16} = BDL1{15-0};
+ let Inst{31-28} = B1;
+ let Inst{27-16} = D1;
let Inst{15-8} = 0;
let Inst{7-0} = op{7-0};
}
@@ -775,11 +829,15 @@ class InstRSLb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
field bits<48> SoftFail = 0;
bits<4> R1;
- bits<24> BDL2;
+ bits<4> B2;
+ bits<12> D2;
+ bits<8> L2;
bits<4> M3;
let Inst{47-40} = op{15-8};
- let Inst{39-16} = BDL2;
+ let Inst{39-32} = L2;
+ let Inst{31-28} = B2;
+ let Inst{27-16} = D2;
let Inst{15-12} = R1;
let Inst{11-8} = M3;
let Inst{7-0} = op{7-0};
@@ -792,12 +850,15 @@ class InstRSYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<4> R1;
bits<4> R3;
- bits<24> BD2;
+ bits<4> B2;
+ bits<20> D2;
let Inst{47-40} = op{15-8};
let Inst{39-36} = R1;
let Inst{35-32} = R3;
- let Inst{31-8} = BD2;
+ let Inst{31-28} = B2;
+ let Inst{27-16} = D2{11-0};
+ let Inst{15-8} = D2{19-12};
let Inst{7-0} = op{7-0};
let Has20BitOffset = 1;
@@ -810,12 +871,15 @@ class InstRSYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<4> R1;
bits<4> M3;
- bits<24> BD2;
+ bits<4> B2;
+ bits<20> D2;
let Inst{47-40} = op{15-8};
let Inst{39-36} = R1;
let Inst{35-32} = M3;
- let Inst{31-8} = BD2;
+ let Inst{31-28} = B2;
+ let Inst{27-16} = D2{11-0};
+ let Inst{15-8} = D2{19-12};
let Inst{7-0} = op{7-0};
let Has20BitOffset = 1;
@@ -826,12 +890,14 @@ class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
field bits<32> Inst;
field bits<32> SoftFail = 0;
- bits<16> BD1;
+ bits<4> B1;
+ bits<12> D1;
bits<8> I2;
let Inst{31-24} = op;
let Inst{23-16} = I2;
- let Inst{15-0} = BD1;
+ let Inst{15-12} = B1;
+ let Inst{11-0} = D1;
}
class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
@@ -839,11 +905,13 @@ class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
field bits<48> Inst;
field bits<48> SoftFail = 0;
- bits<16> BD1;
+ bits<4> B1;
+ bits<12> D1;
bits<16> I2;
let Inst{47-32} = op;
- let Inst{31-16} = BD1;
+ let Inst{31-28} = B1;
+ let Inst{27-16} = D1;
let Inst{15-0} = I2;
}
@@ -852,12 +920,15 @@ class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
field bits<48> Inst;
field bits<48> SoftFail = 0;
- bits<24> BD1;
+ bits<4> B1;
+ bits<20> D1;
bits<8> I2;
let Inst{47-40} = op{15-8};
let Inst{39-32} = I2;
- let Inst{31-8} = BD1;
+ let Inst{31-28} = B1;
+ let Inst{27-16} = D1{11-0};
+ let Inst{15-8} = D1{19-12};
let Inst{7-0} = op{7-0};
let Has20BitOffset = 1;
@@ -870,12 +941,14 @@ class InstSMI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<4> M1;
bits<16> RI2;
- bits<16> BD3;
+ bits<4> B3;
+ bits<12> D3;
let Inst{47-40} = op;
let Inst{39-36} = M1;
let Inst{35-32} = 0;
- let Inst{31-16} = BD3;
+ let Inst{31-28} = B3;
+ let Inst{27-16} = D3;
let Inst{15-0} = RI2;
}
@@ -884,12 +957,18 @@ class InstSSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
field bits<48> Inst;
field bits<48> SoftFail = 0;
- bits<24> BDL1;
- bits<16> BD2;
+ bits<4> B1;
+ bits<12> D1;
+ bits<8> L1;
+ bits<4> B2;
+ bits<12> D2;
let Inst{47-40} = op;
- let Inst{39-16} = BDL1;
- let Inst{15-0} = BD2;
+ let Inst{39-32} = L1;
+ let Inst{31-28} = B1;
+ let Inst{27-16} = D1;
+ let Inst{15-12} = B2;
+ let Inst{11-0} = D2;
}
class InstSSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
@@ -897,14 +976,20 @@ class InstSSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
field bits<48> Inst;
field bits<48> SoftFail = 0;
- bits<20> BDL1;
- bits<20> BDL2;
+ bits<4> B1;
+ bits<12> D1;
+ bits<4> L1;
+ bits<4> B2;
+ bits<12> D2;
+ bits<4> L2;
let Inst{47-40} = op;
- let Inst{39-36} = BDL1{19-16};
- let Inst{35-32} = BDL2{19-16};
- let Inst{31-16} = BDL1{15-0};
- let Inst{15-0} = BDL2{15-0};
+ let Inst{39-36} = L1;
+ let Inst{35-32} = L2;
+ let Inst{31-28} = B1;
+ let Inst{27-16} = D1;
+ let Inst{15-12} = B2;
+ let Inst{11-0} = D2;
}
class InstSSc<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
@@ -912,15 +997,20 @@ class InstSSc<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
field bits<48> Inst;
field bits<48> SoftFail = 0;
- bits<20> BDL1;
- bits<16> BD2;
+ bits<4> B1;
+ bits<12> D1;
+ bits<4> L1;
+ bits<4> B2;
+ bits<12> D2;
bits<4> I3;
let Inst{47-40} = op;
- let Inst{39-36} = BDL1{19-16};
+ let Inst{39-36} = L1;
let Inst{35-32} = I3;
- let Inst{31-16} = BDL1{15-0};
- let Inst{15-0} = BD2;
+ let Inst{31-28} = B1;
+ let Inst{27-16} = D1;
+ let Inst{15-12} = B2;
+ let Inst{11-0} = D2;
}
class InstSSd<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
@@ -928,15 +1018,20 @@ class InstSSd<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
field bits<48> Inst;
field bits<48> SoftFail = 0;
- bits<20> RBD1;
- bits<16> BD2;
+ bits<4> R1;
+ bits<4> B1;
+ bits<12> D1;
+ bits<4> B2;
+ bits<12> D2;
bits<4> R3;
let Inst{47-40} = op;
- let Inst{39-36} = RBD1{19-16};
+ let Inst{39-36} = R1;
let Inst{35-32} = R3;
- let Inst{31-16} = RBD1{15-0};
- let Inst{15-0} = BD2;
+ let Inst{31-28} = B1;
+ let Inst{27-16} = D1;
+ let Inst{15-12} = B2;
+ let Inst{11-0} = D2;
}
class InstSSe<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
@@ -945,15 +1040,19 @@ class InstSSe<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
field bits<48> SoftFail = 0;
bits<4> R1;
- bits<16> BD2;
+ bits<4> B2;
+ bits<12> D2;
bits<4> R3;
- bits<16> BD4;
+ bits<4> B4;
+ bits<12> D4;
let Inst{47-40} = op;
let Inst{39-36} = R1;
let Inst{35-32} = R3;
- let Inst{31-16} = BD2;
- let Inst{15-0} = BD4;
+ let Inst{31-28} = B2;
+ let Inst{27-16} = D2;
+ let Inst{15-12} = B4;
+ let Inst{11-0} = D4;
}
class InstSSf<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
@@ -961,13 +1060,18 @@ class InstSSf<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
field bits<48> Inst;
field bits<48> SoftFail = 0;
- bits<16> BD1;
- bits<24> BDL2;
+ bits<4> B1;
+ bits<12> D1;
+ bits<4> B2;
+ bits<12> D2;
+ bits<8> L2;
let Inst{47-40} = op;
- let Inst{39-32} = BDL2{23-16};
- let Inst{31-16} = BD1;
- let Inst{15-0} = BDL2{15-0};
+ let Inst{39-32} = L2;
+ let Inst{31-28} = B1;
+ let Inst{27-16} = D1;
+ let Inst{15-12} = B2;
+ let Inst{11-0} = D2;
}
class InstSSE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
@@ -975,12 +1079,16 @@ class InstSSE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
field bits<48> Inst;
field bits<48> SoftFail = 0;
- bits<16> BD1;
- bits<16> BD2;
+ bits<4> B1;
+ bits<12> D1;
+ bits<4> B2;
+ bits<12> D2;
let Inst{47-32} = op;
- let Inst{31-16} = BD1;
- let Inst{15-0} = BD2;
+ let Inst{31-28} = B1;
+ let Inst{27-16} = D1;
+ let Inst{15-12} = B2;
+ let Inst{11-0} = D2;
}
class InstSSF<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
@@ -988,15 +1096,19 @@ class InstSSF<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
field bits<48> Inst;
field bits<48> SoftFail = 0;
- bits<16> BD1;
- bits<16> BD2;
+ bits<4> B1;
+ bits<12> D1;
+ bits<4> B2;
+ bits<12> D2;
bits<4> R3;
let Inst{47-40} = op{11-4};
let Inst{39-36} = R3;
let Inst{35-32} = op{3-0};
- let Inst{31-16} = BD1;
- let Inst{15-0} = BD2;
+ let Inst{31-28} = B1;
+ let Inst{27-16} = D1;
+ let Inst{15-12} = B2;
+ let Inst{11-0} = D2;
}
class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
@@ -1004,10 +1116,12 @@ class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
field bits<32> Inst;
field bits<32> SoftFail = 0;
- bits<16> BD2;
+ bits<4> B2;
+ bits<12> D2;
let Inst{31-16} = op;
- let Inst{15-0} = BD2;
+ let Inst{15-12} = B2;
+ let Inst{11-0} = D2;
}
class InstVRIa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
@@ -1493,14 +1607,16 @@ class InstVRSa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
field bits<48> SoftFail = 0;
bits<5> V1;
- bits<16> BD2;
+ bits<4> B2;
+ bits<12> D2;
bits<5> V3;
bits<4> M4;
let Inst{47-40} = op{15-8};
let Inst{39-36} = V1{3-0};
let Inst{35-32} = V3{3-0};
- let Inst{31-16} = BD2;
+ let Inst{31-28} = B2;
+ let Inst{27-16} = D2;
let Inst{15-12} = M4;
let Inst{11} = V1{4};
let Inst{10} = V3{4};
@@ -1514,14 +1630,16 @@ class InstVRSb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
field bits<48> SoftFail = 0;
bits<5> V1;
- bits<16> BD2;
+ bits<4> B2;
+ bits<12> D2;
bits<4> R3;
bits<4> M4;
let Inst{47-40} = op{15-8};
let Inst{39-36} = V1{3-0};
let Inst{35-32} = R3;
- let Inst{31-16} = BD2;
+ let Inst{31-28} = B2;
+ let Inst{27-16} = D2;
let Inst{15-12} = M4;
let Inst{11} = V1{4};
let Inst{10-8} = 0;
@@ -1534,14 +1652,16 @@ class InstVRSc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
field bits<48> SoftFail = 0;
bits<4> R1;
- bits<16> BD2;
+ bits<4> B2;
+ bits<12> D2;
bits<5> V3;
bits<4> M4;
let Inst{47-40} = op{15-8};
let Inst{39-36} = R1;
let Inst{35-32} = V3{3-0};
- let Inst{31-16} = BD2;
+ let Inst{31-28} = B2;
+ let Inst{27-16} = D2;
let Inst{15-12} = M4;
let Inst{11} = 0;
let Inst{10} = V3{4};
@@ -1555,13 +1675,15 @@ class InstVRSd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
field bits<48> SoftFail = 0;
bits<5> V1;
- bits<16> BD2;
+ bits<4> B2;
+ bits<12> D2;
bits<4> R3;
let Inst{47-40} = op{15-8};
let Inst{39-36} = 0;
let Inst{35-32} = R3;
- let Inst{31-16} = BD2;
+ let Inst{31-28} = B2;
+ let Inst{27-16} = D2;
let Inst{15-12} = V1{3-0};
let Inst{11-9} = 0;
let Inst{8} = V1{4};
@@ -1574,15 +1696,19 @@ class InstVRV<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
field bits<48> SoftFail = 0;
bits<5> V1;
- bits<21> VBD2;
+ bits<5> V2;
+ bits<4> B2;
+ bits<12> D2;
bits<4> M3;
let Inst{47-40} = op{15-8};
let Inst{39-36} = V1{3-0};
- let Inst{35-16} = VBD2{19-0};
+ let Inst{35-32} = V2{3-0};
+ let Inst{31-28} = B2;
+ let Inst{27-16} = D2;
let Inst{15-12} = M3;
let Inst{11} = V1{4};
- let Inst{10} = VBD2{20};
+ let Inst{10} = V2{4};
let Inst{9-8} = 0;
let Inst{7-0} = op{7-0};
}
@@ -1593,12 +1719,16 @@ class InstVRX<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
field bits<48> SoftFail = 0;
bits<5> V1;
- bits<20> XBD2;
+ bits<4> X2;
+ bits<4> B2;
+ bits<12> D2;
bits<4> M3;
let Inst{47-40} = op{15-8};
let Inst{39-36} = V1{3-0};
- let Inst{35-16} = XBD2;
+ let Inst{35-32} = X2;
+ let Inst{31-28} = B2;
+ let Inst{27-16} = D2;
let Inst{15-12} = M3;
let Inst{11} = V1{4};
let Inst{10-8} = 0;
@@ -1611,12 +1741,14 @@ class InstVSI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
field bits<48> SoftFail = 0;
bits<5> V1;
- bits<16> BD2;
+ bits<4> B2;
+ bits<12> D2;
bits<8> I3;
let Inst{47-40} = op{15-8};
let Inst{39-32} = I3;
- let Inst{31-16} = BD2;
+ let Inst{31-28} = B2;
+ let Inst{27-16} = D2;
let Inst{15-12} = V1{3-0};
let Inst{11-9} = 0;
let Inst{8} = V1{4};
@@ -1703,14 +1835,11 @@ class DirectiveInsnRS<dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{31-24} = enc{31-24};
}
-// RSE is like RSY except with a 12 bit displacement (instead of 20).
class DirectiveInsnRSE<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRSYa<6, outs, ins, asmstr, pattern> {
+ : InstRSEa<6, outs, ins, asmstr, pattern> {
bits <48> enc;
let Inst{47-40} = enc{47-40};
- let Inst{31-16} = BD2{15-0};
- let Inst{15-8} = 0;
let Inst{7-0} = enc{7-0};
}
@@ -2131,7 +2260,7 @@ class InherentVRIa<string mnemonic, bits<16> opcode, bits<16> value>
class StoreInherentS<string mnemonic, bits<16> opcode,
SDPatternOperator operator, bits<5> bytes>
- : InstS<opcode, (outs), (ins bdaddr12only:$BD2),
+ : InstS<opcode, (outs), (ins (bdaddr12only $B2, $D2):$BD2),
mnemonic#"\t$BD2", [(operator bdaddr12only:$BD2)]> {
let mayStore = 1;
let AccessBytes = bytes;
@@ -2143,7 +2272,8 @@ class SideEffectInherentE<string mnemonic, bits<16>opcode>
class SideEffectInherentS<string mnemonic, bits<16> opcode,
SDPatternOperator operator>
: InstS<opcode, (outs), (ins), mnemonic, [(operator)]> {
- let BD2 = 0;
+ let B2 = 0;
+ let D2 = 0;
}
class SideEffectInherentRRE<string mnemonic, bits<16> opcode>
@@ -2167,7 +2297,7 @@ class CallRR<string mnemonic, bits<8> opcode>
mnemonic#"\t$R1, $R2", []>;
class CallRX<string mnemonic, bits<8> opcode>
- : InstRXa<opcode, (outs), (ins GR64:$R1, bdxaddr12only:$XBD2),
+ : InstRXa<opcode, (outs), (ins GR64:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
mnemonic#"\t$R1, $XBD2", []>;
class CondBranchRI<string mnemonic, bits<12> opcode,
@@ -2229,17 +2359,19 @@ class FixedCondBranchRR<CondVariant V, string mnemonic, bits<8> opcode,
}
class CondBranchRX<string mnemonic, bits<8> opcode>
- : InstRXb<opcode, (outs), (ins cond4:$valid, cond4:$M1, bdxaddr12only:$XBD2),
+ : InstRXb<opcode, (outs),
+ (ins cond4:$valid, cond4:$M1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
!subst("#", "${M1}", mnemonic)#"\t$XBD2", []> {
let CCMaskFirst = 1;
}
class AsmCondBranchRX<string mnemonic, bits<8> opcode>
- : InstRXb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr12only:$XBD2),
+ : InstRXb<opcode, (outs),
+ (ins imm32zx4:$M1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
mnemonic#"\t$M1, $XBD2", []>;
class FixedCondBranchRX<CondVariant V, string mnemonic, bits<8> opcode>
- : InstRXb<opcode, (outs), (ins bdxaddr12only:$XBD2),
+ : InstRXb<opcode, (outs), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
!subst("#", V.suffix, mnemonic)#"\t$XBD2", []> {
let isAsmParserOnly = V.alternate;
let AsmVariantName = V.asmvariant;
@@ -2247,21 +2379,23 @@ class FixedCondBranchRX<CondVariant V, string mnemonic, bits<8> opcode>
}
class CondBranchRXY<string mnemonic, bits<16> opcode>
- : InstRXYb<opcode, (outs), (ins cond4:$valid, cond4:$M1, bdxaddr20only:$XBD2),
+ : InstRXYb<opcode, (outs), (ins cond4:$valid, cond4:$M1,
+ (bdxaddr20only $B2, $D2, $X2):$XBD2),
!subst("#", "${M1}", mnemonic)#"\t$XBD2", []> {
let CCMaskFirst = 1;
let mayLoad = 1;
}
class AsmCondBranchRXY<string mnemonic, bits<16> opcode>
- : InstRXYb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr20only:$XBD2),
+ : InstRXYb<opcode, (outs),
+ (ins imm32zx4:$M1, (bdxaddr20only $B2, $D2, $X2):$XBD2),
mnemonic#"\t$M1, $XBD2", []> {
let mayLoad = 1;
}
class FixedCondBranchRXY<CondVariant V, string mnemonic, bits<16> opcode,
SDPatternOperator operator = null_frag>
- : InstRXYb<opcode, (outs), (ins bdxaddr20only:$XBD2),
+ : InstRXYb<opcode, (outs), (ins (bdxaddr20only $B2, $D2, $X2):$XBD2),
!subst("#", V.suffix, mnemonic)#"\t$XBD2",
[(operator (load bdxaddr20only:$XBD2))]> {
let isAsmParserOnly = V.alternate;
@@ -2381,18 +2515,19 @@ class FixedCmpBranchRRFc<CondVariant V, string mnemonic, bits<16> opcode,
class CmpBranchRRS<string mnemonic, bits<16> opcode,
RegisterOperand cls>
: InstRRS<opcode, (outs),
- (ins cls:$R1, cls:$R2, cond4:$M3, bdaddr12only:$BD4),
+ (ins cls:$R1, cls:$R2, cond4:$M3, (bdaddr12only $B4, $D4):$BD4),
mnemonic#"$M3\t$R1, $R2, $BD4", []>;
class AsmCmpBranchRRS<string mnemonic, bits<16> opcode,
RegisterOperand cls>
: InstRRS<opcode, (outs),
- (ins cls:$R1, cls:$R2, imm32zx4:$M3, bdaddr12only:$BD4),
+ (ins cls:$R1, cls:$R2, imm32zx4:$M3, (bdaddr12only $B4, $D4):$BD4),
mnemonic#"\t$R1, $R2, $M3, $BD4", []>;
class FixedCmpBranchRRS<CondVariant V, string mnemonic, bits<16> opcode,
RegisterOperand cls>
- : InstRRS<opcode, (outs), (ins cls:$R1, cls:$R2, bdaddr12only:$BD4),
+ : InstRRS<opcode, (outs),
+ (ins cls:$R1, cls:$R2, (bdaddr12only $B4, $D4):$BD4),
mnemonic#V.suffix#"\t$R1, $R2, $BD4", []> {
let isAsmParserOnly = V.alternate;
let AsmVariantName = V.asmvariant;
@@ -2409,18 +2544,19 @@ multiclass CmpBranchRRSPair<string mnemonic, bits<16> opcode,
class CmpBranchRIS<string mnemonic, bits<16> opcode,
RegisterOperand cls, ImmOpWithPattern imm>
: InstRIS<opcode, (outs),
- (ins cls:$R1, imm:$I2, cond4:$M3, bdaddr12only:$BD4),
+ (ins cls:$R1, imm:$I2, cond4:$M3, (bdaddr12only $B4, $D4):$BD4),
mnemonic#"$M3\t$R1, $I2, $BD4", []>;
class AsmCmpBranchRIS<string mnemonic, bits<16> opcode,
RegisterOperand cls, ImmOpWithPattern imm>
: InstRIS<opcode, (outs),
- (ins cls:$R1, imm:$I2, imm32zx4:$M3, bdaddr12only:$BD4),
+ (ins cls:$R1, imm:$I2, imm32zx4:$M3, (bdaddr12only $B4, $D4):$BD4),
mnemonic#"\t$R1, $I2, $M3, $BD4", []>;
class FixedCmpBranchRIS<CondVariant V, string mnemonic, bits<16> opcode,
RegisterOperand cls, ImmOpWithPattern imm>
- : InstRIS<opcode, (outs), (ins cls:$R1, imm:$I2, bdaddr12only:$BD4),
+ : InstRIS<opcode, (outs),
+ (ins cls:$R1, imm:$I2, (bdaddr12only $B4, $D4):$BD4),
mnemonic#V.suffix#"\t$R1, $I2, $BD4", []> {
let isAsmParserOnly = V.alternate;
let AsmVariantName = V.asmvariant;
@@ -2436,12 +2572,14 @@ multiclass CmpBranchRISPair<string mnemonic, bits<16> opcode,
class CmpBranchRSYb<string mnemonic, bits<16> opcode,
RegisterOperand cls>
- : InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2, cond4:$M3),
+ : InstRSYb<opcode, (outs),
+ (ins cls:$R1, (bdaddr20only $B2, $D2):$BD2, cond4:$M3),
mnemonic#"$M3\t$R1, $BD2", []>;
class AsmCmpBranchRSYb<string mnemonic, bits<16> opcode,
RegisterOperand cls>
- : InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2, imm32zx4:$M3),
+ : InstRSYb<opcode, (outs),
+ (ins cls:$R1, (bdaddr20only $B2, $D2):$BD2, imm32zx4:$M3),
mnemonic#"\t$R1, $M3, $BD2", []>;
multiclass CmpBranchRSYbPair<string mnemonic, bits<16> opcode,
@@ -2453,7 +2591,7 @@ multiclass CmpBranchRSYbPair<string mnemonic, bits<16> opcode,
class FixedCmpBranchRSYb<CondVariant V, string mnemonic, bits<16> opcode,
RegisterOperand cls>
- : InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2),
+ : InstRSYb<opcode, (outs), (ins cls:$R1, (bdaddr20only $B2, $D2):$BD2),
mnemonic#V.suffix#"\t$R1, $BD2", []> {
let isAsmParserOnly = V.alternate;
let AsmVariantName = V.asmvariant;
@@ -2489,14 +2627,16 @@ class BranchUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
}
class BranchUnaryRX<string mnemonic, bits<8> opcode, RegisterOperand cls>
- : InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
+ : InstRXa<opcode, (outs cls:$R1),
+ (ins cls:$R1src, (bdxaddr12only $B2, $D2, $X2):$XBD2),
mnemonic#"\t$R1, $XBD2", []> {
let Constraints = "$R1 = $R1src";
let DisableEncoding = "$R1src";
}
class BranchUnaryRXY<string mnemonic, bits<16> opcode, RegisterOperand cls>
- : InstRXYa<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr20only:$XBD2),
+ : InstRXYa<opcode, (outs cls:$R1),
+ (ins cls:$R1src, (bdxaddr20only $B2, $D2, $X2):$XBD2),
mnemonic#"\t$R1, $XBD2", []> {
let Constraints = "$R1 = $R1src";
let DisableEncoding = "$R1src";
@@ -2519,7 +2659,7 @@ class BranchBinaryRIEe<string mnemonic, bits<16> opcode, RegisterOperand cls>
class BranchBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls>
: InstRSa<opcode, (outs cls:$R1),
- (ins cls:$R1src, cls:$R3, bdaddr12only:$BD2),
+ (ins cls:$R1src, cls:$R3, (bdaddr12only $B2, $D2):$BD2),
mnemonic#"\t$R1, $R3, $BD2", []> {
let Constraints = "$R1 = $R1src";
let DisableEncoding = "$R1src";
@@ -2527,7 +2667,8 @@ class BranchBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls>
class BranchBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
: InstRSYa<opcode,
- (outs cls:$R1), (ins cls:$R1src, cls:$R3, bdaddr20only:$BD2),
+ (outs cls:$R1),
+ (ins cls:$R1src, cls:$R3, (bdaddr20only $B2, $D2):$BD2),
mnemonic#"\t$R1, $R3, $BD2", []> {
let Constraints = "$R1 = $R1src";
let DisableEncoding = "$R1src";
@@ -2535,14 +2676,14 @@ class BranchBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
class LoadMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
AddressingMode mode = bdaddr12only>
- : InstRSa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
+ : InstRSa<opcode, (outs cls:$R1, cls:$R3), (ins (mode $B2, $D2):$BD2),
mnemonic#"\t$R1, $R3, $BD2", []> {
let mayLoad = 1;
}
class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
AddressingMode mode = bdaddr20only>
- : InstRSYa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
+ : InstRSYa<opcode, (outs cls:$R1, cls:$R3), (ins (mode $B2, $D2):$BD2),
mnemonic#"\t$R1, $R3, $BD2", []> {
let mayLoad = 1;
}
@@ -2559,7 +2700,7 @@ multiclass LoadMultipleRSPair<string mnemonic, bits<8> rsOpcode,
class LoadMultipleSSe<string mnemonic, bits<8> opcode, RegisterOperand cls>
: InstSSe<opcode, (outs cls:$R1, cls:$R3),
- (ins bdaddr12only:$BD2, bdaddr12only:$BD4),
+ (ins (bdaddr12only $B2, $D2):$BD2, (bdaddr12only $B4, $D4):$BD4),
mnemonic#"\t$R1, $R3, $BD2, $BD4", []> {
let mayLoad = 1;
}
@@ -2567,11 +2708,11 @@ class LoadMultipleSSe<string mnemonic, bits<8> opcode, RegisterOperand cls>
multiclass LoadMultipleVRSaAlign<string mnemonic, bits<16> opcode> {
let mayLoad = 1 in {
def Align : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3),
- (ins bdaddr12only:$BD2, imm32zx4:$M4),
+ (ins (bdaddr12only $B2, $D2):$BD2, imm32zx4:$M4),
mnemonic#"\t$V1, $V3, $BD2, $M4", []>;
let M4 = 0 in
def "" : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3),
- (ins bdaddr12only:$BD2),
+ (ins (bdaddr12only $B2, $D2):$BD2),
mnemonic#"\t$V1, $V3, $BD2", []>;
}
}
@@ -2591,7 +2732,7 @@ class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
RegisterOperand cls, bits<5> bytes,
AddressingMode mode = bdxaddr12only>
- : InstRXa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
+ : InstRXa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
mnemonic#"\t$R1, $XBD2",
[(operator cls:$R1, mode:$XBD2)]> {
let OpKey = mnemonic#"r"#cls;
@@ -2603,7 +2744,7 @@ class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
RegisterOperand cls, bits<5> bytes,
AddressingMode mode = bdxaddr20only>
- : InstRXYa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
+ : InstRXYa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
mnemonic#"\t$R1, $XBD2",
[(operator cls:$R1, mode:$XBD2)]> {
let OpKey = mnemonic#"r"#cls;
@@ -2626,7 +2767,8 @@ multiclass StoreRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
class StoreVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
TypedReg tr, bits<5> bytes, bits<4> type = 0>
- : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2),
+ : InstVRX<opcode, (outs),
+ (ins tr.op:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
mnemonic#"\t$V1, $XBD2",
[(operator (tr.vt tr.op:$V1), bdxaddr12only:$XBD2)]> {
let M3 = type;
@@ -2635,7 +2777,8 @@ class StoreVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
}
class StoreVRXGeneric<string mnemonic, bits<16> opcode>
- : InstVRX<opcode, (outs), (ins VR128:$V1, bdxaddr12only:$XBD2, imm32zx4:$M3),
+ : InstVRX<opcode, (outs),
+ (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
mnemonic#"\t$V1, $XBD2, $M3", []> {
let mayStore = 1;
}
@@ -2643,17 +2786,20 @@ class StoreVRXGeneric<string mnemonic, bits<16> opcode>
multiclass StoreVRXAlign<string mnemonic, bits<16> opcode> {
let mayStore = 1, AccessBytes = 16 in {
def Align : InstVRX<opcode, (outs),
- (ins VR128:$V1, bdxaddr12only:$XBD2, imm32zx4:$M3),
+ (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2,
+ imm32zx4:$M3),
mnemonic#"\t$V1, $XBD2, $M3", []>;
let M3 = 0 in
- def "" : InstVRX<opcode, (outs), (ins VR128:$V1, bdxaddr12only:$XBD2),
+ def "" : InstVRX<opcode, (outs),
+ (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
mnemonic#"\t$V1, $XBD2", []>;
}
}
class StoreLengthVRSb<string mnemonic, bits<16> opcode,
SDPatternOperator operator, bits<5> bytes>
- : InstVRSb<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2),
+ : InstVRSb<opcode, (outs),
+ (ins VR128:$V1, GR32:$R3, (bdaddr12only $B2, $D2):$BD2),
mnemonic#"\t$V1, $R3, $BD2",
[(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
let M4 = 0;
@@ -2663,7 +2809,8 @@ class StoreLengthVRSb<string mnemonic, bits<16> opcode,
class StoreLengthVRSd<string mnemonic, bits<16> opcode,
SDPatternOperator operator, bits<5> bytes>
- : InstVRSd<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2),
+ : InstVRSd<opcode, (outs),
+ (ins VR128:$V1, GR32:$R3, (bdaddr12only $B2, $D2):$BD2),
mnemonic#"\t$V1, $R3, $BD2",
[(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
let mayStore = 1;
@@ -2672,7 +2819,8 @@ class StoreLengthVRSd<string mnemonic, bits<16> opcode,
class StoreLengthVSI<string mnemonic, bits<16> opcode,
SDPatternOperator operator, bits<5> bytes>
- : InstVSI<opcode, (outs), (ins VR128:$V1, bdaddr12only:$BD2, imm32zx8:$I3),
+ : InstVSI<opcode, (outs),
+ (ins VR128:$V1, (bdaddr12only $B2, $D2):$BD2, imm32zx8:$I3),
mnemonic#"\t$V1, $BD2, $I3",
[(operator VR128:$V1, imm32zx8:$I3, bdaddr12only:$BD2)]> {
let mayStore = 1;
@@ -2681,14 +2829,14 @@ class StoreLengthVSI<string mnemonic, bits<16> opcode,
class StoreMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
AddressingMode mode = bdaddr12only>
- : InstRSa<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
+ : InstRSa<opcode, (outs), (ins cls:$R1, cls:$R3, (mode $B2, $D2):$BD2),
mnemonic#"\t$R1, $R3, $BD2", []> {
let mayStore = 1;
}
class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
AddressingMode mode = bdaddr20only>
- : InstRSYa<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
+ : InstRSYa<opcode, (outs), (ins cls:$R1, cls:$R3, (mode $B2, $D2):$BD2),
mnemonic#"\t$R1, $R3, $BD2", []> {
let mayStore = 1;
}
@@ -2706,11 +2854,12 @@ multiclass StoreMultipleRSPair<string mnemonic, bits<8> rsOpcode,
multiclass StoreMultipleVRSaAlign<string mnemonic, bits<16> opcode> {
let mayStore = 1 in {
def Align : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3,
- bdaddr12only:$BD2, imm32zx4:$M4),
+ (bdaddr12only $B2, $D2):$BD2,
+ imm32zx4:$M4),
mnemonic#"\t$V1, $V3, $BD2, $M4", []>;
let M4 = 0 in
def "" : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3,
- bdaddr12only:$BD2),
+ (bdaddr12only $B2, $D2):$BD2),
mnemonic#"\t$V1, $V3, $BD2", []>;
}
}
@@ -2723,7 +2872,7 @@ multiclass StoreMultipleVRSaAlign<string mnemonic, bits<16> opcode> {
// only use the StoreSI* instruction if the matched address is suitable.
class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
ImmOpWithPattern imm>
- : InstSI<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
+ : InstSI<opcode, (outs), (ins (mviaddr12pair $B1, $D1):$BD1, imm:$I2),
mnemonic#"\t$BD1, $I2",
[(operator imm:$I2, mviaddr12pair:$BD1)]> {
let mayStore = 1;
@@ -2731,7 +2880,7 @@ class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
ImmOpWithPattern imm>
- : InstSIY<opcode, (outs), (ins mviaddr20pair:$BD1, imm:$I2),
+ : InstSIY<opcode, (outs), (ins (mviaddr20pair $B1, $D1):$BD1, imm:$I2),
mnemonic#"\t$BD1, $I2",
[(operator imm:$I2, mviaddr20pair:$BD1)]> {
let mayStore = 1;
@@ -2739,7 +2888,7 @@ class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
ImmOpWithPattern imm>
- : InstSIL<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
+ : InstSIL<opcode, (outs), (ins (mviaddr12pair $B1, $D1):$BD1, imm:$I2),
mnemonic#"\t$BD1, $I2",
[(operator imm:$I2, mviaddr12pair:$BD1)]> {
let mayStore = 1;
@@ -2756,7 +2905,8 @@ multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
}
class StoreSSE<string mnemonic, bits<16> opcode>
- : InstSSE<opcode, (outs), (ins bdaddr12only:$BD1, bdaddr12only:$BD2),
+ : InstSSE<opcode, (outs),
+ (ins (bdaddr12only $B1, $D1):$BD1, (bdaddr12only $B2, $D2):$BD2),
mnemonic#"\t$BD1, $BD2", []> {
let mayStore = 1;
}
@@ -2764,8 +2914,9 @@ class StoreSSE<string mnemonic, bits<16> opcode>
class CondStoreRSY<string mnemonic, bits<16> opcode,
RegisterOperand cls, bits<5> bytes,
AddressingMode mode = bdaddr20only>
- : InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2, cond4:$valid, cond4:$M3),
- mnemonic#"$M3\t$R1, $BD2", []> {
+ : InstRSYb<opcode, (outs),
+ (ins cls:$R1, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3),
+ mnemonic#"$M3\t$R1, $BD2", []> {
let mayStore = 1;
let AccessBytes = bytes;
let CCMaskLast = 1;
@@ -2776,7 +2927,7 @@ class CondStoreRSY<string mnemonic, bits<16> opcode,
class AsmCondStoreRSY<string mnemonic, bits<16> opcode,
RegisterOperand cls, bits<5> bytes,
AddressingMode mode = bdaddr20only>
- : InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2, imm32zx4:$M3),
+ : InstRSYb<opcode, (outs), (ins cls:$R1, (mode $B2, $D2):$BD2, imm32zx4:$M3),
mnemonic#"\t$R1, $BD2, $M3", []> {
let mayStore = 1;
let AccessBytes = bytes;
@@ -2786,7 +2937,7 @@ class AsmCondStoreRSY<string mnemonic, bits<16> opcode,
class FixedCondStoreRSY<CondVariant V, string mnemonic, bits<16> opcode,
RegisterOperand cls, bits<5> bytes,
AddressingMode mode = bdaddr20only>
- : InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2),
+ : InstRSYb<opcode, (outs), (ins cls:$R1, (mode $B2, $D2):$BD2),
mnemonic#V.suffix#"\t$R1, $BD2", []> {
let mayStore = 1;
let AccessBytes = bytes;
@@ -2823,7 +2974,7 @@ class SideEffectUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
class SideEffectUnaryS<string mnemonic, bits<16> opcode,
SDPatternOperator operator, bits<5> bytes,
AddressingMode mode = bdaddr12only>
- : InstS<opcode, (outs), (ins mode:$BD2),
+ : InstS<opcode, (outs), (ins (mode $B2, $D2):$BD2),
mnemonic#"\t$BD2", [(operator mode:$BD2)]> {
let mayLoad = 1;
let AccessBytes = bytes;
@@ -2832,7 +2983,7 @@ class SideEffectUnaryS<string mnemonic, bits<16> opcode,
class SideEffectUnarySIY<string mnemonic, bits<16> opcode,
bits<5> bytes,
AddressingMode mode = bdaddr20only>
- : InstSIY<opcode, (outs), (ins mode:$BD1),
+ : InstSIY<opcode, (outs), (ins (mode $B1, $D1):$BD1),
mnemonic#"\t$BD1", []> {
let mayLoad = 1;
let AccessBytes = bytes;
@@ -2842,18 +2993,18 @@ class SideEffectUnarySIY<string mnemonic, bits<16> opcode,
class SideEffectAddressS<string mnemonic, bits<16> opcode,
SDPatternOperator operator,
AddressingMode mode = bdaddr12only>
- : InstS<opcode, (outs), (ins mode:$BD2),
+ : InstS<opcode, (outs), (ins (mode $B2, $D2):$BD2),
mnemonic#"\t$BD2", [(operator mode:$BD2)]>;
class LoadAddressRX<string mnemonic, bits<8> opcode,
SDPatternOperator operator, AddressingMode mode>
- : InstRXa<opcode, (outs GR64:$R1), (ins mode:$XBD2),
+ : InstRXa<opcode, (outs GR64:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
mnemonic#"\t$R1, $XBD2",
[(set GR64:$R1, (operator mode:$XBD2))]>;
class LoadAddressRXY<string mnemonic, bits<16> opcode,
SDPatternOperator operator, AddressingMode mode>
- : InstRXYa<opcode, (outs GR64:$R1), (ins mode:$XBD2),
+ : InstRXYa<opcode, (outs GR64:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
mnemonic#"\t$R1, $XBD2",
[(set GR64:$R1, (operator mode:$XBD2))]>;
@@ -2936,7 +3087,7 @@ class CondUnaryRSY<string mnemonic, bits<16> opcode,
SDPatternOperator operator, RegisterOperand cls,
bits<5> bytes, AddressingMode mode = bdaddr20only>
: InstRSYb<opcode, (outs cls:$R1),
- (ins cls:$R1src, mode:$BD2, cond4:$valid, cond4:$M3),
+ (ins cls:$R1src, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3),
mnemonic#"$M3\t$R1, $BD2",
[(set cls:$R1,
(z_select_ccmask (operator bdaddr20only:$BD2), cls:$R1src,
@@ -2957,7 +3108,8 @@ class CondUnaryRSY<string mnemonic, bits<16> opcode,
class AsmCondUnaryRSY<string mnemonic, bits<16> opcode,
RegisterOperand cls, bits<5> bytes,
AddressingMode mode = bdaddr20only>
- : InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2, imm32zx4:$M3),
+ : InstRSYb<opcode, (outs cls:$R1),
+ (ins cls:$R1src, (mode $B2, $D2):$BD2, imm32zx4:$M3),
mnemonic#"\t$R1, $BD2, $M3", []> {
let mayLoad = 1;
let AccessBytes = bytes;
@@ -2969,7 +3121,7 @@ class AsmCondUnaryRSY<string mnemonic, bits<16> opcode,
class FixedCondUnaryRSY<CondVariant V, string mnemonic, bits<16> opcode,
RegisterOperand cls, bits<5> bytes,
AddressingMode mode = bdaddr20only>
- : InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2),
+ : InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, (mode $B2, $D2):$BD2),
mnemonic#V.suffix#"\t$R1, $BD2", []> {
let Constraints = "$R1 = $R1src";
let DisableEncoding = "$R1src";
@@ -2992,7 +3144,7 @@ multiclass CondUnaryRSYPair<string mnemonic, bits<16> opcode,
class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
RegisterOperand cls, bits<5> bytes,
AddressingMode mode = bdxaddr12only>
- : InstRXa<opcode, (outs cls:$R1), (ins mode:$XBD2),
+ : InstRXa<opcode, (outs cls:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
mnemonic#"\t$R1, $XBD2",
[(set cls:$R1, (operator mode:$XBD2))]> {
let OpKey = mnemonic#"r"#cls;
@@ -3003,7 +3155,7 @@ class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
RegisterOperand cls, bits<5> bytes>
- : InstRXE<opcode, (outs cls:$R1), (ins bdxaddr12only:$XBD2),
+ : InstRXE<opcode, (outs cls:$R1), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
mnemonic#"\t$R1, $XBD2",
[(set cls:$R1, (operator bdxaddr12only:$XBD2))]> {
let OpKey = mnemonic#"r"#cls;
@@ -3016,7 +3168,7 @@ class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
RegisterOperand cls, bits<5> bytes,
AddressingMode mode = bdxaddr20only>
- : InstRXYa<opcode, (outs cls:$R1), (ins mode:$XBD2),
+ : InstRXYa<opcode, (outs cls:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
mnemonic#"\t$R1, $XBD2",
[(set cls:$R1, (operator mode:$XBD2))]> {
let OpKey = mnemonic#"r"#cls;
@@ -3110,7 +3262,7 @@ multiclass UnaryExtraVRRaSPairGeneric<string mnemonic, bits<16> opcode> {
class UnaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
TypedReg tr, bits<5> bytes, bits<4> type = 0>
- : InstVRX<opcode, (outs tr.op:$V1), (ins bdxaddr12only:$XBD2),
+ : InstVRX<opcode, (outs tr.op:$V1), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
mnemonic#"\t$V1, $XBD2",
[(set (tr.vt tr.op:$V1), (operator bdxaddr12only:$XBD2))]> {
let M3 = type;
@@ -3119,7 +3271,8 @@ class UnaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
}
class UnaryVRXGeneric<string mnemonic, bits<16> opcode>
- : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
+ : InstVRX<opcode, (outs VR128:$V1),
+ (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
mnemonic#"\t$V1, $XBD2, $M3", []> {
let mayLoad = 1;
}
@@ -3127,22 +3280,23 @@ class UnaryVRXGeneric<string mnemonic, bits<16> opcode>
multiclass UnaryVRXAlign<string mnemonic, bits<16> opcode> {
let mayLoad = 1, AccessBytes = 16 in {
def Align : InstVRX<opcode, (outs VR128:$V1),
- (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
+ (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
mnemonic#"\t$V1, $XBD2, $M3", []>;
let M3 = 0 in
- def "" : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2),
+ def "" : InstVRX<opcode, (outs VR128:$V1),
+ (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
mnemonic#"\t$V1, $XBD2", []>;
}
}
class SideEffectBinaryRX<string mnemonic, bits<8> opcode,
RegisterOperand cls>
- : InstRXa<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
+ : InstRXa<opcode, (outs), (ins cls:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
mnemonic#"\t$R1, $XBD2", []>;
class SideEffectBinaryRXY<string mnemonic, bits<16> opcode,
RegisterOperand cls>
- : InstRXYa<opcode, (outs), (ins cls:$R1, bdxaddr20only:$XBD2),
+ : InstRXYa<opcode, (outs), (ins cls:$R1, (bdxaddr20only $B2, $D2, $X2):$XBD2),
mnemonic#"\t$R1, $XBD2", []>;
class SideEffectBinaryRILPC<string mnemonic, bits<12> opcode,
@@ -3181,29 +3335,33 @@ class SideEffectBinaryIE<string mnemonic, bits<16> opcode,
mnemonic#"\t$I1, $I2", []>;
class SideEffectBinarySI<string mnemonic, bits<8> opcode, Operand imm>
- : InstSI<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
+ : InstSI<opcode, (outs), (ins (bdaddr12only $B1, $D1):$BD1, imm:$I2),
mnemonic#"\t$BD1, $I2", []>;
class SideEffectBinarySIL<string mnemonic, bits<16> opcode,
SDPatternOperator operator, ImmOpWithPattern imm>
- : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
+ : InstSIL<opcode, (outs), (ins (bdaddr12only $B1, $D1):$BD1, imm:$I2),
mnemonic#"\t$BD1, $I2", [(operator bdaddr12only:$BD1, imm:$I2)]>;
class SideEffectBinarySSa<string mnemonic, bits<8> opcode>
- : InstSSa<opcode, (outs), (ins bdladdr12onlylen8:$BDL1, bdaddr12only:$BD2),
+ : InstSSa<opcode, (outs), (ins (bdladdr12onlylen8 $B1, $D1, $L1):$BDL1,
+ (bdaddr12only $B2, $D2):$BD2),
mnemonic#"\t$BDL1, $BD2", []>;
class SideEffectBinarySSb<string mnemonic, bits<8> opcode>
: InstSSb<opcode,
- (outs), (ins bdladdr12onlylen4:$BDL1, bdladdr12onlylen4:$BDL2),
+ (outs), (ins (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1,
+ (bdladdr12onlylen4 $B2, $D2, $L2):$BDL2),
mnemonic#"\t$BDL1, $BDL2", []>;
class SideEffectBinarySSf<string mnemonic, bits<8> opcode>
- : InstSSf<opcode, (outs), (ins bdaddr12only:$BD1, bdladdr12onlylen8:$BDL2),
+ : InstSSf<opcode, (outs), (ins (bdaddr12only $B1, $D1):$BD1,
+ (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2),
mnemonic#"\t$BD1, $BDL2", []>;
class SideEffectBinarySSE<string mnemonic, bits<16> opcode>
- : InstSSE<opcode, (outs), (ins bdaddr12only:$BD1, bdaddr12only:$BD2),
+ : InstSSE<opcode, (outs),
+ (ins (bdaddr12only $B1, $D1):$BD1, (bdaddr12only $B2, $D2):$BD2),
mnemonic#"\t$BD1, $BD2", []>;
class SideEffectBinaryMemMemRR<string mnemonic, bits<8> opcode,
@@ -3511,7 +3669,8 @@ class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
class BinaryRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
RegisterOperand cls>
- : InstRSa<opcode, (outs cls:$R1), (ins cls:$R1src, shift12only:$BD2),
+ : InstRSa<opcode, (outs cls:$R1),
+ (ins cls:$R1src, (shift12only $B2, $D2):$BD2),
mnemonic#"\t$R1, $BD2",
[(set cls:$R1, (operator cls:$R1src, shift12only:$BD2))]> {
let R3 = 0;
@@ -3521,7 +3680,7 @@ class BinaryRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
class BinaryRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
RegisterOperand cls>
- : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, shift20only:$BD2),
+ : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, (shift20only $B2, $D2):$BD2),
mnemonic#"\t$R1, $R3, $BD2",
[(set cls:$R1, (operator cls:$R3, shift20only:$BD2))]>;
@@ -3538,7 +3697,7 @@ multiclass BinaryRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
class BinaryRSL<string mnemonic, bits<16> opcode, RegisterOperand cls>
: InstRSLb<opcode, (outs cls:$R1),
- (ins bdladdr12onlylen8:$BDL2, imm32zx4:$M3),
+ (ins (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2, imm32zx4:$M3),
mnemonic#"\t$R1, $BDL2, $M3", []> {
let mayLoad = 1;
}
@@ -3546,7 +3705,7 @@ class BinaryRSL<string mnemonic, bits<16> opcode, RegisterOperand cls>
class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
AddressingMode mode = bdxaddr12only>
- : InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
+ : InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, (mode $B2, $D2, $X2):$XBD2),
mnemonic#"\t$R1, $XBD2",
[(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
let OpKey = mnemonic#"r"#cls;
@@ -3559,7 +3718,8 @@ class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
- : InstRXE<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
+ : InstRXE<opcode, (outs cls:$R1),
+ (ins cls:$R1src, (bdxaddr12only $B2, $D2, $X2):$XBD2),
mnemonic#"\t$R1, $XBD2",
[(set cls:$R1, (operator cls:$R1src,
(load bdxaddr12only:$XBD2)))]> {
@@ -3575,7 +3735,8 @@ class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
class BinaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
RegisterOperand cls1, RegisterOperand cls2,
SDPatternOperator load, bits<5> bytes>
- : InstRXF<opcode, (outs cls1:$R1), (ins cls2:$R3, bdxaddr12only:$XBD2),
+ : InstRXF<opcode, (outs cls1:$R1),
+ (ins cls2:$R3, (bdxaddr12only $B2, $D2, $X2):$XBD2),
mnemonic#"\t$R1, $R3, $XBD2",
[(set cls1:$R1, (operator cls2:$R3, (load bdxaddr12only:$XBD2)))]> {
let OpKey = mnemonic#"r"#cls;
@@ -3587,7 +3748,8 @@ class BinaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
AddressingMode mode = bdxaddr20only>
- : InstRXYa<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
+ : InstRXYa<opcode, (outs cls:$R1),
+ (ins cls:$R1src, (mode $B2, $D2, $X2):$XBD2),
mnemonic#"\t$R1, $XBD2",
[(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
let OpKey = mnemonic#"r"#cls;
@@ -3613,7 +3775,7 @@ multiclass BinaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
Operand imm, AddressingMode mode = bdaddr12only>
- : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
+ : InstSI<opcode, (outs), (ins (mode $B1, $D1):$BD1, imm:$I2),
mnemonic#"\t$BD1, $I2",
[(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
let mayLoad = 1;
@@ -3622,7 +3784,7 @@ class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
Operand imm, AddressingMode mode = bdaddr20only>
- : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
+ : InstSIY<opcode, (outs), (ins (mode $B1, $D1):$BD1, imm:$I2),
mnemonic#"\t$BD1, $I2",
[(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
let mayLoad = 1;
@@ -3641,7 +3803,8 @@ multiclass BinarySIPair<string mnemonic, bits<8> siOpcode,
}
class BinarySSF<string mnemonic, bits<12> opcode, RegisterOperand cls>
- : InstSSF<opcode, (outs cls:$R3), (ins bdaddr12pair:$BD1, bdaddr12pair:$BD2),
+ : InstSSF<opcode, (outs cls:$R3),
+ (ins (bdaddr12pair $B1, $D1):$BD1, (bdaddr12pair $B2, $D2):$BD2),
mnemonic#"\t$R3, $BD1, $BD2", []> {
let mayLoad = 1;
}
@@ -3849,7 +4012,8 @@ class BinaryVRRk<string mnemonic, bits<16> opcode>
class BinaryVRSa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
TypedReg tr1, TypedReg tr2, bits<4> type>
- : InstVRSa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, shift12only:$BD2),
+ : InstVRSa<opcode, (outs tr1.op:$V1),
+ (ins tr2.op:$V3, (shift12only $B2, $D2):$BD2),
mnemonic#"\t$V1, $V3, $BD2",
[(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V3),
shift12only:$BD2))]> {
@@ -3858,12 +4022,13 @@ class BinaryVRSa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
class BinaryVRSaGeneric<string mnemonic, bits<16> opcode>
: InstVRSa<opcode, (outs VR128:$V1),
- (ins VR128:$V3, shift12only:$BD2, imm32zx4:$M4),
+ (ins VR128:$V3, (shift12only $B2, $D2):$BD2, imm32zx4:$M4),
mnemonic#"\t$V1, $V3, $BD2, $M4", []>;
class BinaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
bits<5> bytes>
- : InstVRSb<opcode, (outs VR128:$V1), (ins GR32:$R3, bdaddr12only:$BD2),
+ : InstVRSb<opcode, (outs VR128:$V1),
+ (ins GR32:$R3, (bdaddr12only $B2, $D2):$BD2),
mnemonic#"\t$V1, $R3, $BD2",
[(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> {
let M4 = 0;
@@ -3873,20 +4038,22 @@ class BinaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
class BinaryVRSc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
TypedReg tr, bits<4> type>
- : InstVRSc<opcode, (outs GR64:$R1), (ins tr.op:$V3, shift12only:$BD2),
- mnemonic#"\t$R1, $V3, $BD2",
- [(set GR64:$R1, (operator (tr.vt tr.op:$V3), shift12only:$BD2))]> {
+ : InstVRSc<opcode, (outs GR64:$R1),
+ (ins tr.op:$V3, (shift12only $B2, $D2):$BD2),
+ mnemonic#"\t$R1, $V3, $BD2",
+ [(set GR64:$R1, (operator (tr.vt tr.op:$V3), shift12only:$BD2))]> {
let M4 = type;
}
class BinaryVRScGeneric<string mnemonic, bits<16> opcode>
: InstVRSc<opcode, (outs GR64:$R1),
- (ins VR128:$V3, shift12only:$BD2, imm32zx4: $M4),
+ (ins VR128:$V3, (shift12only $B2, $D2):$BD2, imm32zx4: $M4),
mnemonic#"\t$R1, $V3, $BD2, $M4", []>;
class BinaryVRSd<string mnemonic, bits<16> opcode, SDPatternOperator operator,
bits<5> bytes>
- : InstVRSd<opcode, (outs VR128:$V1), (ins GR32:$R3, bdaddr12only:$BD2),
+ : InstVRSd<opcode, (outs VR128:$V1),
+ (ins GR32:$R3, (bdaddr12only $B2, $D2):$BD2),
mnemonic#"\t$V1, $R3, $BD2",
[(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> {
let mayLoad = 1;
@@ -3895,7 +4062,8 @@ class BinaryVRSd<string mnemonic, bits<16> opcode, SDPatternOperator operator,
class BinaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
TypedReg tr, bits<5> bytes>
- : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
+ : InstVRX<opcode, (outs VR128:$V1),
+ (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
mnemonic#"\t$V1, $XBD2, $M3",
[(set (tr.vt tr.op:$V1), (operator bdxaddr12only:$XBD2,
imm32zx4_timm:$M3))]> {
@@ -3905,7 +4073,7 @@ class BinaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
class StoreBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
bits<5> bytes, AddressingMode mode = bdaddr12only>
- : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
+ : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
mnemonic#"\t$R1, $M3, $BD2", []> {
let mayStore = 1;
let AccessBytes = bytes;
@@ -3913,7 +4081,7 @@ class StoreBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
class StoreBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
bits<5> bytes, AddressingMode mode = bdaddr20only>
- : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
+ : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
mnemonic#"\t$R1, $M3, $BD2", []> {
let mayStore = 1;
let AccessBytes = bytes;
@@ -3933,14 +4101,16 @@ multiclass StoreBinaryRSPair<string mnemonic, bits<8> rsOpcode,
class StoreBinaryRSL<string mnemonic, bits<16> opcode, RegisterOperand cls>
: InstRSLb<opcode, (outs),
- (ins cls:$R1, bdladdr12onlylen8:$BDL2, imm32zx4:$M3),
+ (ins cls:$R1, (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2,
+ imm32zx4:$M3),
mnemonic#"\t$R1, $BDL2, $M3", []> {
let mayStore = 1;
}
class BinaryVSI<string mnemonic, bits<16> opcode, SDPatternOperator operator,
bits<5> bytes>
- : InstVSI<opcode, (outs VR128:$V1), (ins bdaddr12only:$BD2, imm32zx8:$I3),
+ : InstVSI<opcode, (outs VR128:$V1),
+ (ins (bdaddr12only $B2, $D2):$BD2, imm32zx8:$I3),
mnemonic#"\t$V1, $BD2, $I3",
[(set VR128:$V1, (operator imm32zx8:$I3, bdaddr12only:$BD2))]> {
let mayLoad = 1;
@@ -3949,7 +4119,8 @@ class BinaryVSI<string mnemonic, bits<16> opcode, SDPatternOperator operator,
class StoreBinaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
ImmOpWithPattern index>
- : InstVRV<opcode, (outs), (ins VR128:$V1, bdvaddr12only:$VBD2, index:$M3),
+ : InstVRV<opcode, (outs),
+ (ins VR128:$V1, (bdvaddr12only $B2, $D2, $V2):$VBD2, index:$M3),
mnemonic#"\t$V1, $VBD2, $M3", []> {
let mayStore = 1;
let AccessBytes = bytes;
@@ -3958,7 +4129,8 @@ class StoreBinaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
class StoreBinaryVRX<string mnemonic, bits<16> opcode,
SDPatternOperator operator, TypedReg tr, bits<5> bytes,
ImmOpWithPattern index>
- : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2, index:$M3),
+ : InstVRX<opcode, (outs),
+ (ins tr.op:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2, index:$M3),
mnemonic#"\t$V1, $XBD2, $M3",
[(operator (tr.vt tr.op:$V1), bdxaddr12only:$XBD2, index:$M3)]> {
let mayStore = 1;
@@ -3968,7 +4140,8 @@ class StoreBinaryVRX<string mnemonic, bits<16> opcode,
class MemoryBinarySSd<string mnemonic, bits<8> opcode,
RegisterOperand cls>
: InstSSd<opcode, (outs),
- (ins bdraddr12only:$RBD1, bdaddr12only:$BD2, cls:$R3),
+ (ins (bdraddr12only $B1, $D1, $R1):$RBD1,
+ (bdaddr12only $B2, $D2):$BD2, cls:$R3),
mnemonic#"\t$RBD1, $BD2, $R3", []>;
class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
@@ -4023,7 +4196,7 @@ class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
AddressingMode mode = bdxaddr12only>
- : InstRXa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
+ : InstRXa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
mnemonic#"\t$R1, $XBD2",
[(set CC, (operator cls:$R1, (load mode:$XBD2)))]> {
let OpKey = mnemonic#"r"#cls;
@@ -4035,7 +4208,7 @@ class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
- : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
+ : InstRXE<opcode, (outs), (ins cls:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
mnemonic#"\t$R1, $XBD2",
[(set CC, (operator cls:$R1, (load bdxaddr12only:$XBD2)))]> {
let OpKey = mnemonic#"r"#cls;
@@ -4049,7 +4222,7 @@ class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
AddressingMode mode = bdxaddr20only>
- : InstRXYa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
+ : InstRXYa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
mnemonic#"\t$R1, $XBD2",
[(set CC, (operator cls:$R1, (load mode:$XBD2)))]> {
let OpKey = mnemonic#"r"#cls;
@@ -4074,7 +4247,7 @@ multiclass CompareRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
class CompareRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
bits<5> bytes, AddressingMode mode = bdaddr12only>
- : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
+ : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
mnemonic#"\t$R1, $M3, $BD2", []> {
let mayLoad = 1;
let AccessBytes = bytes;
@@ -4082,7 +4255,7 @@ class CompareRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
class CompareRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
bits<5> bytes, AddressingMode mode = bdaddr20only>
- : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
+ : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
mnemonic#"\t$R1, $M3, $BD2", []> {
let mayLoad = 1;
let AccessBytes = bytes;
@@ -4100,7 +4273,8 @@ multiclass CompareRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
class CompareSSb<string mnemonic, bits<8> opcode>
: InstSSb<opcode,
- (outs), (ins bdladdr12onlylen4:$BDL1, bdladdr12onlylen4:$BDL2),
+ (outs), (ins (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1,
+ (bdladdr12onlylen4 $B2, $D2, $L2):$BDL2),
mnemonic#"\t$BDL1, $BDL2", []> {
let isCompare = 1;
let mayLoad = 1;
@@ -4109,7 +4283,7 @@ class CompareSSb<string mnemonic, bits<8> opcode>
class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
SDPatternOperator load, ImmOpWithPattern imm,
AddressingMode mode = bdaddr12only>
- : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
+ : InstSI<opcode, (outs), (ins (mode $B1, $D1):$BD1, imm:$I2),
mnemonic#"\t$BD1, $I2",
[(set CC, (operator (load mode:$BD1), imm:$I2))]> {
let isCompare = 1;
@@ -4118,7 +4292,7 @@ class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
SDPatternOperator load, ImmOpWithPattern imm>
- : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
+ : InstSIL<opcode, (outs), (ins (bdaddr12only $B1, $D1):$BD1, imm:$I2),
mnemonic#"\t$BD1, $I2",
[(set CC, (operator (load bdaddr12only:$BD1), imm:$I2))]> {
let isCompare = 1;
@@ -4128,7 +4302,7 @@ class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
class CompareSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
SDPatternOperator load, ImmOpWithPattern imm,
AddressingMode mode = bdaddr20only>
- : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
+ : InstSIY<opcode, (outs), (ins (mode $B1, $D1):$BD1, imm:$I2),
mnemonic#"\t$BD1, $I2",
[(set CC, (operator (load mode:$BD1), imm:$I2))]> {
let isCompare = 1;
@@ -4185,12 +4359,13 @@ class CompareVRRh<string mnemonic, bits<16> opcode>
class TestInherentS<string mnemonic, bits<16> opcode,
SDPatternOperator operator>
: InstS<opcode, (outs), (ins), mnemonic, [(set CC, (operator))]> {
- let BD2 = 0;
+ let B2 = 0;
+ let D2 = 0;
}
class TestRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
RegisterOperand cls>
- : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
+ : InstRXE<opcode, (outs), (ins cls:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
mnemonic#"\t$R1, $XBD2",
[(set CC, (operator cls:$R1, bdxaddr12only:$XBD2))]> {
let M3 = 0;
@@ -4198,12 +4373,12 @@ class TestRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
class TestBinarySIL<string mnemonic, bits<16> opcode,
SDPatternOperator operator, ImmOpWithPattern imm>
- : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
+ : InstSIL<opcode, (outs), (ins (bdaddr12only $B1, $D1):$BD1, imm:$I2),
mnemonic#"\t$BD1, $I2",
[(set CC, (operator bdaddr12only:$BD1, imm:$I2))]>;
class TestRSL<string mnemonic, bits<16> opcode>
- : InstRSLa<opcode, (outs), (ins bdladdr12onlylen4:$BDL1),
+ : InstRSLa<opcode, (outs), (ins (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1),
mnemonic#"\t$BDL1", []> {
let mayLoad = 1;
}
@@ -4213,8 +4388,8 @@ class TestVRRg<string mnemonic, bits<16> opcode>
mnemonic#"\t$V1", []>;
class SideEffectTernarySSc<string mnemonic, bits<8> opcode>
- : InstSSc<opcode, (outs), (ins bdladdr12onlylen4:$BDL1,
- shift12only:$BD2, imm32zx4:$I3),
+ : InstSSc<opcode, (outs), (ins (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1,
+ (shift12only $B2, $D2):$BD2, imm32zx4:$I3),
mnemonic#"\t$BDL1, $BD2, $I3", []>;
class SideEffectTernaryRRFa<string mnemonic, bits<16> opcode,
@@ -4289,7 +4464,8 @@ multiclass SideEffectTernaryMemMemRRFcOpt<string mnemonic, bits<16> opcode,
class SideEffectTernarySSF<string mnemonic, bits<12> opcode,
RegisterOperand cls>
: InstSSF<opcode, (outs),
- (ins bdaddr12only:$BD1, bdaddr12only:$BD2, cls:$R3),
+ (ins (bdaddr12only $B1, $D1):$BD1,
+ (bdaddr12only $B2, $D2):$BD2, cls:$R3),
mnemonic#"\t$BD1, $BD2, $R3", []>;
class TernaryRRFa<string mnemonic, bits<16> opcode,
@@ -4328,7 +4504,7 @@ class TernaryRRD<string mnemonic, bits<16> opcode, SDPatternOperator operator,
class TernaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
bits<5> bytes, AddressingMode mode = bdaddr12only>
: InstRSb<opcode, (outs cls:$R1),
- (ins cls:$R1src, imm32zx4:$M3, mode:$BD2),
+ (ins cls:$R1src, imm32zx4:$M3, (mode $B2, $D2):$BD2),
mnemonic#"\t$R1, $M3, $BD2", []> {
let Constraints = "$R1 = $R1src";
@@ -4340,7 +4516,7 @@ class TernaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
class TernaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
bits<5> bytes, AddressingMode mode = bdaddr20only>
: InstRSYb<opcode, (outs cls:$R1),
- (ins cls:$R1src, imm32zx4:$M3, mode:$BD2),
+ (ins cls:$R1src, imm32zx4:$M3, (mode $B2, $D2):$BD2),
mnemonic#"\t$R1, $M3, $BD2", []> {
let Constraints = "$R1 = $R1src";
@@ -4362,19 +4538,19 @@ multiclass TernaryRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
class SideEffectTernaryRS<string mnemonic, bits<8> opcode,
RegisterOperand cls1, RegisterOperand cls2>
: InstRSa<opcode, (outs),
- (ins cls1:$R1, cls2:$R3, bdaddr12only:$BD2),
+ (ins cls1:$R1, cls2:$R3, (bdaddr12only $B2, $D2):$BD2),
mnemonic#"\t$R1, $R3, $BD2", []>;
class SideEffectTernaryRSY<string mnemonic, bits<16> opcode,
RegisterOperand cls1, RegisterOperand cls2>
: InstRSYa<opcode, (outs),
- (ins cls1:$R1, cls2:$R3, bdaddr20only:$BD2),
+ (ins cls1:$R1, cls2:$R3, (bdaddr20only $B2, $D2):$BD2),
mnemonic#"\t$R1, $R3, $BD2", []>;
class SideEffectTernaryMemMemRS<string mnemonic, bits<8> opcode,
RegisterOperand cls1, RegisterOperand cls2>
: InstRSa<opcode, (outs cls1:$R1, cls2:$R3),
- (ins cls1:$R1src, cls2:$R3src, shift12only:$BD2),
+ (ins cls1:$R1src, cls2:$R3src, (shift12only $B2, $D2):$BD2),
mnemonic#"\t$R1, $R3, $BD2", []> {
let Constraints = "$R1 = $R1src, $R3 = $R3src";
let DisableEncoding = "$R1src, $R3src";
@@ -4383,7 +4559,7 @@ class SideEffectTernaryMemMemRS<string mnemonic, bits<8> opcode,
class SideEffectTernaryMemMemRSY<string mnemonic, bits<16> opcode,
RegisterOperand cls1, RegisterOperand cls2>
: InstRSYa<opcode, (outs cls1:$R1, cls2:$R3),
- (ins cls1:$R1src, cls2:$R3src, shift20only:$BD2),
+ (ins cls1:$R1src, cls2:$R3src, (shift20only $B2, $D2):$BD2),
mnemonic#"\t$R1, $R3, $BD2", []> {
let Constraints = "$R1 = $R1src, $R3 = $R3src";
let DisableEncoding = "$R1src, $R3src";
@@ -4393,7 +4569,7 @@ class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
RegisterOperand cls1, RegisterOperand cls2,
SDPatternOperator load, bits<5> bytes>
: InstRXF<opcode, (outs cls1:$R1),
- (ins cls2:$R1src, cls2:$R3, bdxaddr12only:$XBD2),
+ (ins cls2:$R1src, cls2:$R3, (bdxaddr12only $B2, $D2, $X2):$XBD2),
mnemonic#"\t$R1, $R3, $XBD2",
[(set cls1:$R1, (operator cls2:$R1src, cls2:$R3,
(load bdxaddr12only:$XBD2)))]> {
@@ -4593,7 +4769,7 @@ class TernaryVRReFloatGeneric<string mnemonic, bits<16> opcode>
class TernaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
TypedReg tr1, TypedReg tr2, RegisterOperand cls, bits<4> type>
: InstVRSb<opcode, (outs tr1.op:$V1),
- (ins tr2.op:$V1src, cls:$R3, shift12only:$BD2),
+ (ins tr2.op:$V1src, cls:$R3, (shift12only $B2, $D2):$BD2),
mnemonic#"\t$V1, $R3, $BD2",
[(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V1src),
cls:$R3,
@@ -4615,7 +4791,8 @@ class TernaryVRRj<string mnemonic, bits<16> opcode>
class TernaryVRSbGeneric<string mnemonic, bits<16> opcode>
: InstVRSb<opcode, (outs VR128:$V1),
- (ins VR128:$V1src, GR64:$R3, shift12only:$BD2, imm32zx4:$M4),
+ (ins VR128:$V1src, GR64:$R3, (shift12only $B2, $D2):$BD2,
+ imm32zx4:$M4),
mnemonic#"\t$V1, $R3, $BD2, $M4", []> {
let Constraints = "$V1 = $V1src";
let DisableEncoding = "$V1src";
@@ -4624,7 +4801,7 @@ class TernaryVRSbGeneric<string mnemonic, bits<16> opcode>
class TernaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
ImmOpWithPattern index>
: InstVRV<opcode, (outs VR128:$V1),
- (ins VR128:$V1src, bdvaddr12only:$VBD2, index:$M3),
+ (ins VR128:$V1src, (bdvaddr12only $B2, $D2, $V2):$VBD2, index:$M3),
mnemonic#"\t$V1, $VBD2, $M3", []> {
let Constraints = "$V1 = $V1src";
let DisableEncoding = "$V1src";
@@ -4635,7 +4812,7 @@ class TernaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
class TernaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
TypedReg tr1, TypedReg tr2, bits<5> bytes, ImmOpWithPattern index>
: InstVRX<opcode, (outs tr1.op:$V1),
- (ins tr2.op:$V1src, bdxaddr12only:$XBD2, index:$M3),
+ (ins tr2.op:$V1src, (bdxaddr12only $B2, $D2, $X2):$XBD2, index:$M3),
mnemonic#"\t$V1, $XBD2, $M3",
[(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V1src),
bdxaddr12only:$XBD2,
@@ -4764,12 +4941,13 @@ multiclass SideEffectQuaternaryRRFbOpt<string mnemonic, bits<16> opcode,
class SideEffectQuaternarySSe<string mnemonic, bits<8> opcode,
RegisterOperand cls>
: InstSSe<opcode, (outs),
- (ins cls:$R1, bdaddr12only:$BD2, cls:$R3, bdaddr12only:$BD4),
+ (ins cls:$R1, (bdaddr12only $B2, $D2):$BD2, cls:$R3,
+ (bdaddr12only $B4, $D4):$BD4),
mnemonic#"\t$R1, $BD2, $R3, $BD4", []>;
class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
RegisterOperand cls, AddressingMode mode = bdaddr20only>
- : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2),
+ : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, (mode $B2, $D2):$BD2),
mnemonic#"\t$R1, $R3, $BD2",
[(set cls:$R1, (operator mode:$BD2, cls:$R3))]> {
let mayLoad = 1;
@@ -4788,7 +4966,8 @@ class CmpSwapRRE<string mnemonic, bits<16> opcode,
class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
RegisterOperand cls, AddressingMode mode = bdaddr12only>
- : InstRSa<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
+ : InstRSa<opcode, (outs cls:$R1),
+ (ins cls:$R1src, cls:$R3, (mode $B2, $D2):$BD2),
mnemonic#"\t$R1, $R3, $BD2",
[(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
let Constraints = "$R1 = $R1src";
@@ -4799,7 +4978,8 @@ class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
RegisterOperand cls, AddressingMode mode = bdaddr20only>
- : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
+ : InstRSYa<opcode, (outs cls:$R1),
+ (ins cls:$R1src, cls:$R3, (mode $B2, $D2):$BD2),
mnemonic#"\t$R1, $R3, $BD2",
[(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
let Constraints = "$R1 = $R1src";
@@ -4829,7 +5009,8 @@ class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
}
class PrefetchRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator>
- : InstRXYb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr20only:$XBD2),
+ : InstRXYb<opcode, (outs),
+ (ins imm32zx4:$M1, (bdxaddr20only $B2, $D2, $X2):$XBD2),
mnemonic#"\t$M1, $XBD2",
[(operator imm32zx4_timm:$M1, bdxaddr20only:$XBD2)]>;
@@ -4846,7 +5027,8 @@ class PrefetchRILPC<string mnemonic, bits<12> opcode,
class BranchPreloadSMI<string mnemonic, bits<8> opcode>
: InstSMI<opcode, (outs),
- (ins imm32zx4:$M1, brtarget16bpp:$RI2, bdxaddr12only:$BD3),
+ (ins imm32zx4:$M1, brtarget16bpp:$RI2,
+ (bdaddr12only $B3, $D3):$BD3),
mnemonic#"\t$M1, $RI2, $BD3", []>;
class BranchPreloadMII<string mnemonic, bits<8> opcode>
@@ -4892,7 +5074,7 @@ class UnaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
class UnaryRXYPseudo<string key, SDPatternOperator operator,
RegisterOperand cls, bits<5> bytes,
AddressingMode mode = bdxaddr20only>
- : Pseudo<(outs cls:$R1), (ins mode:$XBD2),
+ : Pseudo<(outs cls:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
[(set cls:$R1, (operator mode:$XBD2))]> {
let OpKey = key#"r"#cls;
let OpType = "mem";
@@ -4944,7 +5126,7 @@ multiclass BinaryRIAndKPseudo<string key, SDPatternOperator operator,
// Mapping: <INSN>R -> MemFoldPseudo -> <INSN>
class MemFoldPseudo<string mnemonic, RegisterOperand cls, bits<5> bytes,
AddressingMode mode>
- : Pseudo<(outs cls:$R1), (ins cls:$R2, mode:$XBD2), []> {
+ : Pseudo<(outs cls:$R1), (ins cls:$R2, (mode $B2, $D2, $X2):$XBD2), []> {
let OpKey = !subst("mscrk", "msrkc",
!subst("msgcrk", "msgrkc",
mnemonic#"rk"#cls));
@@ -4966,7 +5148,8 @@ class MemFoldPseudo_FP<string mnemonic, RegisterOperand cls, bits<5> bytes,
class MemFoldPseudo_FPTern<string mnemonic, RegisterOperand cls, bits<5> bytes,
AddressingMode mode>
- : Pseudo<(outs cls:$R1), (ins cls:$R2, cls:$R3, mode:$XBD2), []> {
+ : Pseudo<(outs cls:$R1),
+ (ins cls:$R2, cls:$R3, (mode $B2, $D2, $X2):$XBD2), []> {
let OpKey = mnemonic#"r"#"MemFold"#cls;
let OpType = "mem";
let MemKey = mnemonic#cls;
@@ -4981,7 +5164,7 @@ class MemFoldPseudo_FPTern<string mnemonic, RegisterOperand cls, bits<5> bytes,
class MemFoldPseudo_CondMove<string mnemonic, RegisterOperand cls, bits<5> bytes,
AddressingMode mode>
: Pseudo<(outs cls:$R1),
- (ins cls:$R2, mode:$XBD2, cond4:$valid, cond4:$M3), []> {
+ (ins cls:$R2, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3), []> {
let OpKey = !subst("loc", "sel", mnemonic)#"r"#cls;
let OpType = "mem";
let MemKey = mnemonic#cls;
@@ -5003,7 +5186,7 @@ class CompareRIPseudo<SDPatternOperator operator, RegisterOperand cls,
class CompareRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
SDPatternOperator load, bits<5> bytes,
AddressingMode mode = bdxaddr20only>
- : Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
+ : Pseudo<(outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
[(set CC, (operator cls:$R1, (load mode:$XBD2)))]> {
let mayLoad = 1;
let Has20BitOffset = 1;
@@ -5013,7 +5196,7 @@ class CompareRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
// Like TestBinarySIL, but expanded later.
class TestBinarySILPseudo<SDPatternOperator operator, ImmOpWithPattern imm>
- : Pseudo<(outs), (ins bdaddr12only:$BD1, imm:$I2),
+ : Pseudo<(outs), (ins (bdaddr12only $B1, $D1):$BD1, imm:$I2),
[(set CC, (operator bdaddr12only:$BD1, imm:$I2))]>;
// Like CondBinaryRRF, but expanded after RA depending on the choice of
@@ -5066,7 +5249,7 @@ class CondUnaryRSYPseudo<string mnemonic, SDPatternOperator operator,
RegisterOperand cls, bits<5> bytes,
AddressingMode mode = bdaddr20only>
: Pseudo<(outs cls:$R1),
- (ins cls:$R1src, mode:$BD2, cond4:$valid, cond4:$R3),
+ (ins cls:$R1src, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$R3),
[(set cls:$R1,
(z_select_ccmask (operator mode:$BD2), cls:$R1src,
cond4:$valid, cond4:$R3))]> {
@@ -5085,7 +5268,8 @@ class CondUnaryRSYPseudo<string mnemonic, SDPatternOperator operator,
// register.
class CondStoreRSYPseudo<RegisterOperand cls, bits<5> bytes,
AddressingMode mode = bdaddr20only>
- : Pseudo<(outs), (ins cls:$R1, mode:$BD2, cond4:$valid, cond4:$R3), []> {
+ : Pseudo<(outs),
+ (ins cls:$R1, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$R3), []> {
let mayStore = 1;
let AccessBytes = bytes;
let CCMaskLast = 1;
@@ -5094,7 +5278,7 @@ class CondStoreRSYPseudo<RegisterOperand cls, bits<5> bytes,
// Like StoreRXY, but expanded after RA depending on the choice of register.
class StoreRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
bits<5> bytes, AddressingMode mode = bdxaddr20only>
- : Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
+ : Pseudo<(outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
[(operator cls:$R1, mode:$XBD2)]> {
let mayStore = 1;
let Has20BitOffset = 1;
@@ -5211,13 +5395,13 @@ class UnaryAliasVRR<SDPatternOperator operator, TypedReg tr1, TypedReg tr2>
// An alias of a UnaryVRX, but with
diff erent register sizes.
class UnaryAliasVRX<SDPatternOperator operator, TypedReg tr,
AddressingMode mode = bdxaddr12only>
- : Alias<6, (outs tr.op:$V1), (ins mode:$XBD2),
+ : Alias<6, (outs tr.op:$V1), (ins (mode $B2, $D2, $X2):$XBD2),
[(set (tr.vt tr.op:$V1), (operator mode:$XBD2))]>;
// An alias of a StoreVRX, but with
diff erent register sizes.
class StoreAliasVRX<SDPatternOperator operator, TypedReg tr,
AddressingMode mode = bdxaddr12only>
- : Alias<6, (outs), (ins tr.op:$V1, mode:$XBD2),
+ : Alias<6, (outs), (ins tr.op:$V1, (mode $B2, $D2, $X2):$XBD2),
[(operator (tr.vt tr.op:$V1), mode:$XBD2)]>;
// An alias of a BinaryRI, but with
diff erent register sizes.
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index aa5c181f55f412..87eb3838aec412 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -112,7 +112,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
// condition mask set to "never". NOP_bare can't be an InstAlias since it
// would need R0D hard coded which is not part of ADDR64BitRegClass.
def NOP : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>;
-let isAsmParserOnly = 1, hasNoSchedulingInfo = 1, M1 = 0, XBD2 = 0 in
+let isAsmParserOnly = 1, hasNoSchedulingInfo = 1, M1 = 0, X2 = 0, B2 = 0, D2 = 0 in
def NOP_bare : InstRXb<0x47,(outs), (ins), "nop", []>;
def NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>;
def NOPR_bare : InstAlias<"nopr", (BCRAsm 0, R0D), 0>;
@@ -2237,7 +2237,7 @@ let isCodeGenOnly = 1, hasSideEffects = 1 in {
def InsnRIS : DirectiveInsnRIS<(outs),
(ins imm64zx48:$enc, AnyReg:$R1,
imm32sx8:$I2, imm32zx4:$M3,
- bdaddr12only:$BD4),
+ (bdaddr12only $B4, $D4):$BD4),
".insn ris,$enc,$R1,$I2,$M3,$BD4", []>;
def InsnRR : DirectiveInsnRR<(outs),
(ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2),
@@ -2252,15 +2252,15 @@ let isCodeGenOnly = 1, hasSideEffects = 1 in {
def InsnRRS : DirectiveInsnRRS<(outs),
(ins imm64zx48:$enc, AnyReg:$R1,
AnyReg:$R2, imm32zx4:$M3,
- bdaddr12only:$BD4),
+ (bdaddr12only $B4, $D4):$BD4),
".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>;
def InsnRS : DirectiveInsnRS<(outs),
(ins imm64zx32:$enc, AnyReg:$R1,
- AnyReg:$R3, bdaddr12only:$BD2),
+ AnyReg:$R3, (bdaddr12only $B2, $D2):$BD2),
".insn rs,$enc,$R1,$R3,$BD2", []>;
def InsnRSE : DirectiveInsnRSE<(outs),
(ins imm64zx48:$enc, AnyReg:$R1,
- AnyReg:$R3, bdaddr12only:$BD2),
+ AnyReg:$R3, (bdaddr12only $B2, $D2):$BD2),
".insn rse,$enc,$R1,$R3,$BD2", []>;
def InsnRSI : DirectiveInsnRSI<(outs),
(ins imm64zx48:$enc, AnyReg:$R1,
@@ -2268,47 +2268,47 @@ let isCodeGenOnly = 1, hasSideEffects = 1 in {
".insn rsi,$enc,$R1,$R3,$RI2", []>;
def InsnRSY : DirectiveInsnRSY<(outs),
(ins imm64zx48:$enc, AnyReg:$R1,
- AnyReg:$R3, bdaddr20only:$BD2),
+ AnyReg:$R3, (bdaddr20only $B2, $D2):$BD2),
".insn rsy,$enc,$R1,$R3,$BD2", []>;
def InsnRX : DirectiveInsnRX<(outs), (ins imm64zx32:$enc, AnyReg:$R1,
- bdxaddr12only:$XBD2),
+ (bdxaddr12only $B2, $D2, $X2):$XBD2),
".insn rx,$enc,$R1,$XBD2", []>;
def InsnRXE : DirectiveInsnRXE<(outs), (ins imm64zx48:$enc, AnyReg:$R1,
- bdxaddr12only:$XBD2),
+ (bdxaddr12only $B2, $D2, $X2):$XBD2),
".insn rxe,$enc,$R1,$XBD2", []>;
def InsnRXF : DirectiveInsnRXF<(outs),
(ins imm64zx48:$enc, AnyReg:$R1,
- AnyReg:$R3, bdxaddr12only:$XBD2),
+ AnyReg:$R3, (bdxaddr12only $B2, $D2, $X2):$XBD2),
".insn rxf,$enc,$R1,$R3,$XBD2", []>;
def InsnRXY : DirectiveInsnRXY<(outs), (ins imm64zx48:$enc, AnyReg:$R1,
- bdxaddr20only:$XBD2),
+ (bdxaddr20only $B2, $D2, $X2):$XBD2),
".insn rxy,$enc,$R1,$XBD2", []>;
def InsnS : DirectiveInsnS<(outs),
- (ins imm64zx32:$enc, bdaddr12only:$BD2),
+ (ins imm64zx32:$enc, (bdaddr12only $B2, $D2):$BD2),
".insn s,$enc,$BD2", []>;
def InsnSI : DirectiveInsnSI<(outs),
- (ins imm64zx32:$enc, bdaddr12only:$BD1,
+ (ins imm64zx32:$enc, (bdaddr12only $B1, $D1):$BD1,
imm32sx8:$I2),
".insn si,$enc,$BD1,$I2", []>;
def InsnSIY : DirectiveInsnSIY<(outs),
(ins imm64zx48:$enc,
- bdaddr20only:$BD1, imm32zx8:$I2),
+ (bdaddr20only $B1, $D1):$BD1, imm32zx8:$I2),
".insn siy,$enc,$BD1,$I2", []>;
def InsnSIL : DirectiveInsnSIL<(outs),
- (ins imm64zx48:$enc, bdaddr12only:$BD1,
+ (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1,
imm32zx16:$I2),
".insn sil,$enc,$BD1,$I2", []>;
def InsnSS : DirectiveInsnSS<(outs),
- (ins imm64zx48:$enc, bdraddr12only:$RBD1,
- bdaddr12only:$BD2, AnyReg:$R3),
+ (ins imm64zx48:$enc, (bdraddr12only $B1, $D1, $R1):$RBD1,
+ (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
".insn ss,$enc,$RBD1,$BD2,$R3", []>;
def InsnSSE : DirectiveInsnSSE<(outs),
(ins imm64zx48:$enc,
- bdaddr12only:$BD1,bdaddr12only:$BD2),
+ (bdaddr12only $B1, $D1):$BD1,(bdaddr12only $B2, $D2):$BD2),
".insn sse,$enc,$BD1,$BD2", []>;
def InsnSSF : DirectiveInsnSSF<(outs),
- (ins imm64zx48:$enc, bdaddr12only:$BD1,
- bdaddr12only:$BD2, AnyReg:$R3),
+ (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1,
+ (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
".insn ssf,$enc,$BD1,$BD2,$R3", []>;
def InsnVRI : DirectiveInsnVRI<(outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
@@ -2321,19 +2321,19 @@ let isCodeGenOnly = 1, hasSideEffects = 1 in {
".insn vrr,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>;
def InsnVRS : DirectiveInsnVRS<(outs),
(ins imm64zx48:$enc, AnyReg:$R1, VR128:$V3,
- bdaddr12only:$BD2, imm32zx4:$M4),
+ (bdaddr12only $B2, $D2):$BD2, imm32zx4:$M4),
".insn vrs,$enc,$BD2,$M4", []>;
def InsnVRV : DirectiveInsnVRV<(outs),
(ins imm64zx48:$enc, VR128:$V1,
- bdvaddr12only:$VBD2, imm32zx4:$M3),
+ (bdvaddr12only $B2, $D2, $V2):$VBD2, imm32zx4:$M3),
".insn vrv,$enc,$V1,$VBD2,$M3", []>;
def InsnVRX : DirectiveInsnVRX<(outs),
(ins imm64zx48:$enc, VR128:$V1,
- bdxaddr12only:$XBD2, imm32zx4:$M3),
+ (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
".insn vrx,$enc,$V1,$XBD2,$M3", []>;
def InsnVSI : DirectiveInsnVSI<(outs),
(ins imm64zx48:$enc, VR128:$V1,
- bdaddr12only:$BD2, imm32zx8:$I3),
+ (bdaddr12only $B2, $D2):$BD2, imm32zx8:$I3),
".insn vsi,$enc,$V1,$BD2,$I3", []>;
}
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrVector.td b/llvm/lib/Target/SystemZ/SystemZInstrVector.td
index 2e9524a44f9c1a..82863d7838a953 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrVector.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrVector.td
@@ -113,7 +113,7 @@ let Predicates = [FeatureVector] in {
// Load count to block boundary.
let Defs = [CC] in
def LCBB : InstRXE<0xE727, (outs GR32:$R1),
- (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
+ (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
"lcbb\t$R1, $XBD2, $M3",
[(set GR32:$R1, (int_s390_lcbb bdxaddr12only:$XBD2,
imm32zx4_timm:$M3))]>;
diff --git a/llvm/lib/Target/SystemZ/SystemZOperands.td b/llvm/lib/Target/SystemZ/SystemZOperands.td
index 8ad30b422b3dbd..a363d8752d2ab8 100644
--- a/llvm/lib/Target/SystemZ/SystemZOperands.td
+++ b/llvm/lib/Target/SystemZ/SystemZOperands.td
@@ -105,9 +105,6 @@ class AddressOperand<string bitsize, string dispsize, string length,
string format, dag operands>
: Operand<!cast<ValueType>("i"#bitsize)> {
let PrintMethod = "print"#format#"Operand";
- let EncoderMethod = "get"#format#dispsize#length#"Encoding";
- let DecoderMethod =
- "decode"#format#bitsize#"Disp"#dispsize#length#"Operand";
let OperandType = "OPERAND_MEMORY";
let MIOperandInfo = operands;
let ParserMatchClass =
@@ -151,7 +148,7 @@ class BDLMode<string type, string bitsize, string dispsize, string suffix,
"BDLAddr",
(ops !cast<RegisterOperand>("ADDR"#bitsize),
!cast<Operand>("disp"#dispsize#"imm"#bitsize),
- !cast<Operand>("imm"#bitsize))>;
+ !cast<Operand>("len"#lensize#"imm"#bitsize))>;
// A BDMode paired with a register length operand.
class BDRMode<string type, string bitsize, string dispsize, string suffix>
@@ -507,8 +504,18 @@ defm imm64zx48 : Immediate<i64, [{
return isUInt<64>(N->getZExtValue());
}], UIMM48, "U48Imm">;
-let OperandType = "OPERAND_IMMEDIATE" in
- def imm64 : ImmLeaf<i64, [{}]>, Operand<i64>;
+class Imm64 : ImmLeaf<i64, [{}]>, Operand<i64> {
+ let OperandType = "OPERAND_IMMEDIATE";
+}
+def imm64 : Imm64;
+def len4imm64 : Imm64 {
+ let EncoderMethod = "getLenEncoding<4>";
+ let DecoderMethod = "decodeLenOperand<4>";
+}
+def len8imm64 : Imm64 {
+ let EncoderMethod = "getLenEncoding<8>";
+ let DecoderMethod = "decodeLenOperand<8>";
+}
//===----------------------------------------------------------------------===//
// Floating-point immediates
@@ -583,12 +590,18 @@ def pcrel32 : PCRelAddress<i64, "pcrel32", PCRel32> {
//===----------------------------------------------------------------------===//
// 12-bit displacement operands.
-def disp12imm32 : Operand<i32>;
-def disp12imm64 : Operand<i64>;
+let EncoderMethod = "getDisp12Encoding",
+ DecoderMethod = "decodeU12ImmOperand" in {
+ def disp12imm32 : Operand<i32>;
+ def disp12imm64 : Operand<i64>;
+}
// 20-bit displacement operands.
-def disp20imm32 : Operand<i32>;
-def disp20imm64 : Operand<i64>;
+let EncoderMethod = "getDisp20Encoding",
+ DecoderMethod = "decodeS20ImmOperand" in {
+ def disp20imm32 : Operand<i32>;
+ def disp20imm64 : Operand<i64>;
+}
def BDAddr32Disp12 : AddressAsmOperand<"BDAddr", "32", "12">;
def BDAddr32Disp20 : AddressAsmOperand<"BDAddr", "32", "20">;
diff --git a/llvm/test/MC/Disassembler/SystemZ/insns-pcrel.txt b/llvm/test/MC/Disassembler/SystemZ/insns-pcrel.txt
index 71060538ebca5f..ef1d0f1970d166 100644
--- a/llvm/test/MC/Disassembler/SystemZ/insns-pcrel.txt
+++ b/llvm/test/MC/Disassembler/SystemZ/insns-pcrel.txt
@@ -1732,7 +1732,7 @@
0xec 0x0f 0x00 0x00 0x00 0x7f
# 0x000009d8:
-# CHECK: exrl %r0, 0x9d8
+# CHECK: exrl 0, 0x9d8
0xc6 0x00 0x00 0x00 0x00 0x00
# 0x000009de:
@@ -1740,7 +1740,7 @@
0xc6 0xf0 0x00 0x00 0x00 0x00
# 0x000009e4:
-# CHECK: exrl %r0, 0x9e2
+# CHECK: exrl 0, 0x9e2
0xc6 0x00 0xff 0xff 0xff 0xff
# 0x000009ea:
@@ -1748,7 +1748,7 @@
0xc6 0xf0 0xff 0xff 0xff 0xff
# 0x000009f0:
-# CHECK: exrl %r0, 0xffffffff000009f0
+# CHECK: exrl 0, 0xffffffff000009f0
0xc6 0x00 0x80 0x00 0x00 0x00
# 0x000009f6:
@@ -1756,7 +1756,7 @@
0xc6 0xf0 0x80 0x00 0x00 0x00
# 0x000009fc:
-# CHECK: exrl %r0, 0x1000009fa
+# CHECK: exrl 0, 0x1000009fa
0xc6 0x00 0x7f 0xff 0xff 0xff
# 0x00000a02:
diff --git a/llvm/test/MC/Disassembler/SystemZ/insns.txt b/llvm/test/MC/Disassembler/SystemZ/insns.txt
index 2ca19363c46b15..f2f942ed5d36eb 100644
--- a/llvm/test/MC/Disassembler/SystemZ/insns.txt
+++ b/llvm/test/MC/Disassembler/SystemZ/insns.txt
@@ -1258,6 +1258,9 @@
# CHECK: balr %r0, %r15
0x05 0x0f
+# CHECK: balr %r1, 0
+0x05 0x10
+
# CHECK: balr %r14, %r9
0x05 0xe9
@@ -1288,6 +1291,9 @@
# CHECK: basr %r0, %r15
0x0d 0x0f
+# CHECK: basr %r1, 0
+0x0d 0x10
+
# CHECK: basr %r14, %r9
0x0d 0xe9
@@ -1300,6 +1306,9 @@
# CHECK: bassm %r0, %r15
0x0c 0x0f
+# CHECK: bassm %r1, 0
+0x0c 0x10
+
# CHECK: bassm %r14, %r9
0x0c 0xe9
@@ -1408,7 +1417,7 @@
# CHECK: bnhr %r1
0x07 0xd1
-# CHECK: bnor %r0
+# CHECK: bnor 0
0x07 0xe0
# CHECK: br %r1
@@ -1525,6 +1534,9 @@
# CHECK: bsm %r0, %r15
0x0b 0x0f
+# CHECK: bsm %r1, 0
+0x0b 0x10
+
# CHECK: bsm %r14, %r9
0x0b 0xe9
@@ -6535,22 +6547,22 @@
# CHECK: etnd %r7
0xb2 0xec 0x00 0x70
-# CHECK: ex %r0, 0
+# CHECK: ex 0, 0
0x44 0x00 0x00 0x00
-# CHECK: ex %r0, 4095
+# CHECK: ex 0, 4095
0x44 0x00 0x0f 0xff
-# CHECK: ex %r0, 0(%r1)
+# CHECK: ex 0, 0(%r1)
0x44 0x00 0x10 0x00
-# CHECK: ex %r0, 0(%r15)
+# CHECK: ex 0, 0(%r15)
0x44 0x00 0xf0 0x00
-# CHECK: ex %r0, 4095(%r1,%r15)
+# CHECK: ex 0, 4095(%r1,%r15)
0x44 0x01 0xff 0xff
-# CHECK: ex %r0, 4095(%r15,%r1)
+# CHECK: ex 0, 4095(%r15,%r1)
0x44 0x0f 0x1f 0xff
# CHECK: ex %r15, 0
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