[PATCH] D155229: [RISCV] Add VL nodes and VP patterns for unary zvbb instructions

[Luke Lau via Phabricator via llvm-commits]

luke updated this revision to Diff 540378.
luke added a comment.

Restrict VL nodes to integers


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155229/new/

https://reviews.llvm.org/D155229

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
  llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
  llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
  llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
  llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
  llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll

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