[PATCH] D155229: [RISCV] Add VL nodes and VP patterns for unary zvbb instructions

[Luke Lau via Phabricator via llvm-commits]

luke added a comment.

In D155229#4498771 <https://reviews.llvm.org/D155229#4498771>, @craig.topper wrote:

>> They
>
> also aren't restricted to integers as presumably we can use these for
> floats too later.
>
> Wouldn't we use a bitcast for that?

Ah you're right, didn't realise the langref specified that they must be integer vectors. Doesn't look like the vp intrinsics enforce this though, the verifier accepts this and crashes when trying to expand it:

  llvm
  declare <vscale x 2 x float> @llvm.vp.ctlz.nxv2f32(<vscale x 2 x float>, i1 immarg, <vscale x 2 x i1>, i32)
  
  define <vscale x 2 x float> @vp_ctlz_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
    %v = call <vscale x 2 x float> @llvm.vp.ctlz.nxv2f32(<vscale x 2 x float> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
    ret <vscale x 2 x float> %v
  }


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https://reviews.llvm.org/D155229