[PATCH] D155283: [RISCV] Cleanups in CORE-V (xcv) extensions

[Simon Cook via Phabricator via llvm-commits]

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This is a mostly NFC change cleaning up and clarifying components of the
in-tree CORE-V (xcv*) extensions following discussions on the remaining
extensions.

This makes the following changes to the xcbitmanip and xcvmac support:

1. Add missing extensions from RISCVISAInfo, such that they can be supported in clang's -march option.
2. Clarify the extension version number is 1.0.0 in documentation.
3. Clarify the extensions are by OpenHW Group, and the capitilization of the CORE-V extension family.
4. Add CORE-V to extension name in RISCVFeatures, both to be consistent with other vendors, and also better distinguish e.g. CORE-V bit manipulation vs RISC-V's standard Zb extensions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D155283

Files:
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/test/MC/RISCV/corev/XCVbitmanip.s
  llvm/test/MC/RISCV/corev/XCVmac-valid.s

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