[PATCH] D154858: [AMDGPU] Add llvm.amdgcn.wave.reduce.umin/umax Intrinsic.

[Yashwant Singh via Phabricator via llvm-commits]

yassingh added a comment.

Need MIR tests for pseudo expansion



================
Comment at: llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp:4521-4528
+      OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, DstSize);
+      if (isSALUMapping(MI))
+        OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, OpSize);
+      else {
+        OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, OpSize);
+      }
+      break;
----------------



================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:4113
+    } else {
+      // To reduce the VGPR using iterative approach, we need to iterative
+      // over all the active lanes. Lowering consists of ComputeLoop,
----------------
typo `iterative`


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:4115
+      // over all the active lanes. Lowering consists of ComputeLoop,
+      // which iterative over only active lanes. We use copy of EXEC register
+      // as induction variable and every active lane modifies it using bitset0
----------------
same


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:4150
+      unsigned MovOpc = IsWave32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
+      unsigned ExecOpc = IsWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
+
----------------
ExecReg


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D154858/new/

https://reviews.llvm.org/D154858