[PATCH] D155216: [RISCV] Add initial SDNode patterns for unary zvbb instructions

[Luke Lau via Phabricator via llvm-commits]

luke updated this revision to Diff 540092.
luke added a comment.

Fix typo and add predicate to patterns


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155216/new/

https://reviews.llvm.org/D155216

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
  llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll

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