[PATCH] D154281: [CodeGen] Store SP adjustment in MachineBasicBlock. NFCI.

[Oliver Stannard via Phabricator via llvm-commits]

olista01 added a comment.

Hi, this change has caused a regression in one of our tests:

  #include <assert.h>
  #include <alloca.h>
  #include <stdio.h>
  
  struct S51 {
    int M50[20];
  };
  
  struct S2 {
    int a, b;
  };
  
  struct S2 F38(struct S51 P4) {
    int V0 = 14;
    __asm("" : "+r"(V0));
    char *V1 = (char *)alloca(V0);
    __asm volatile("" : : "r"(V1));
  
    struct S2 result = {1, 2};
    return result;
  }
  
  signed int main(void) {
    struct S51 P4 = {0};
    struct S2 ret = F38(P4);
  
    assert(ret.a == 1);
    assert(ret.b == 2);
  
    return 0;
  }



  $ /work/ac6/build-armclang/bin/clang --target=arm--none-eabi -march=armv7-m -c test.c -O1 -o - -S
  ...
  main:
          .fnstart
  @ %bb.0:                                @ %entry
          .save   {r4, r6, r7, lr}
          push    {r4, r6, r7, lr}
          .setfp  r7, sp, #8
          add     r7, sp, #8
          .pad    #160
          sub     sp, #160
          add     r4, sp, #80
          mov     r0, r4
          movs    r1, #80
          bl      __aeabi_memclr4
          mov     r0, sp
          add.w   r1, r4, #12
          movs    r2, #68
  .LBB1_1:                                @ %entry
                                          @ =>This Inner Loop Header: Depth=1
          ldr     r3, [r1], #4
          subs    r2, #4
          str     r3, [r0], #4
          bne     .LBB1_1
  @ %bb.2:                                @ %entry
          add     r3, sp, #152
          ldm     r3, {r1, r2, r3}
          add     r0, sp, #144
          bl      F38
          ldr     r0, [sp, #144]
          cmp     r0, #1
          bne     .LBB1_5
  @ %bb.3:                                @ %cond.end
          ldr     r0, [sp, #76]
          cmp     r0, #2
          ittt    eq
          moveq   r0, #0
          addeq   sp, #160
          popeq   {r4, r6, r7, pc}
  .LBB1_4:                                @ %cond.false5
          movw    r0, :lower16:.L.str.2
          movw    r1, :lower16:.L.str.1
          movt    r0, :upper16:.L.str.2
          movt    r1, :upper16:.L.str.1
          movs    r2, #30
          bl      __aeabi_assert
  .LBB1_5:                                @ %cond.false
          movw    r0, :lower16:.L.str
          movw    r1, :lower16:.L.str.1
          movt    r0, :upper16:.L.str
          movt    r1, :upper16:.L.str.1
          movs    r2, #29
          bl      __aeabi_assert
  .Lfunc_end1:
  ...

The bug is in the code generated for main: according to the ARM ABI, the return type of `F38` should be passed in memory provided by the caller, with a pointer to it passed in `r0`. The code for main sets this to `SP+144`, and reads the first member of the struct from that address, but then reads the second member from `SP+76`, instead of `SP+148`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154281/new/

https://reviews.llvm.org/D154281