[PATCH] D155140: [RISCV] Add isMoveReg to vmv1r/vmv2r/vmv4r/vmv8r.v.

Wang Pengcheng via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Jul 12 19:37:35 PDT 2023

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wangpc added a comment.

Is it possible to add a MIR test that performs DCE on vector registers?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D155140/new/

https://reviews.llvm.org/D155140

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