[PATCH] D154936: [AArch64] Improve cost of umull from known bits

[Dave Green via Phabricator via llvm-commits]

dmgreen marked an inline comment as done.
dmgreen added a comment.

Thanks



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Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:1957-1958
 
-  // Exit early if DstTy is not a vector type whose elements are at least
-  // 16-bits wide. SVE doesn't generally have the same set of instructions to
+  // Exit early if DstTy is not a vector type whose elements are one of [i16,
+  // i32, i64]. SVE doesn't generally have the same set of instructions to
   // perform an extend with the add/sub/mul. There are SMULLB style
----------------
samtebbs wrote:
> Is checking for i16, i32 and i64 not the same as checking if the elements are at least 16 bits wide? Could we encounter 128 bit here?
Yeah it's aiming to rule out strange types like i23 too, but doing that earlier so we don't get further into this function before realizing we dont have a legal operation for types like those.


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Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:1988-1992
+    if (isa<SExtInst>(Args[0]) && isa<SExtInst>(Args[1])) {
+      if (!SrcTy)
+        SrcTy =
+            toVectorTy(cast<Instruction>(Args[0])->getOperand(0)->getType());
+    } else if (isa<ZExtInst>(Args[0]) && isa<ZExtInst>(Args[1])) {
----------------
samtebbs wrote:
> Perhaps these two if statements could be combined.
Sounds good.


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  https://reviews.llvm.org/D154936/new/

https://reviews.llvm.org/D154936