[PATCH] D154936: [AArch64] Improve cost of umull from known bits

[Sam Tebbs via Phabricator via llvm-commits]

samtebbs accepted this revision.
samtebbs added a comment.
This revision is now accepted and ready to land.

Looks good to me with a couple of questions.



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Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:1957-1958
 
-  // Exit early if DstTy is not a vector type whose elements are at least
-  // 16-bits wide. SVE doesn't generally have the same set of instructions to
+  // Exit early if DstTy is not a vector type whose elements are one of [i16,
+  // i32, i64]. SVE doesn't generally have the same set of instructions to
   // perform an extend with the add/sub/mul. There are SMULLB style
----------------
Is checking for i16, i32 and i64 not the same as checking if the elements are at least 16 bits wide? Could we encounter 128 bit here?


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Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:1988-1992
+    if (isa<SExtInst>(Args[0]) && isa<SExtInst>(Args[1])) {
+      if (!SrcTy)
+        SrcTy =
+            toVectorTy(cast<Instruction>(Args[0])->getOperand(0)->getType());
+    } else if (isa<ZExtInst>(Args[0]) && isa<ZExtInst>(Args[1])) {
----------------
Perhaps these two if statements could be combined.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154936/new/

https://reviews.llvm.org/D154936