[PATCH] D154687: [RISCV] Narrow types of index operand matched pattern (shl (zext), C).

[Yeting Kuo via Phabricator via llvm-commits]

fakepaper56 added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:10643
+  SDValue Src = N0.getOperand(0);
+  EVT SrcVT = Src.getValueType();
+  unsigned SrcElen = SrcVT.getScalarSizeInBits();
----------------
craig.topper wrote:
> Do we have tests where SrcVT is not an MVT?
I think test_vloxei6 and test_vloxei7 in `llvm/test/CodeGen/RISCV/rvv/narrow-shift-extend.ll` are the case.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:10647
+  unsigned NewElen = PowerOf2Ceil(SrcElen + ShAmtV);
+  NewElen = std::max(NewElen, 8U);
+
----------------
craig.topper wrote:
> Do we have tests for the case where NewElen is less than 8?
I think test_vloxei7 in llvm/test/CodeGen/RISCV/rvv/narrow-shift-extend.ll is the case.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D154687/new/

https://reviews.llvm.org/D154687