[PATCH] D154687: [RISCV] Narrow types of index operand matched pattern (shl (zext), C).

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:10643
+  SDValue Src = N0.getOperand(0);
+  EVT SrcVT = Src.getValueType();
+  unsigned SrcElen = SrcVT.getScalarSizeInBits();
----------------
Do we have tests where SrcVT is not an MVT?


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:10647
+  unsigned NewElen = PowerOf2Ceil(SrcElen + ShAmtV);
+  NewElen = std::max(NewElen, 8U);
+
----------------
Do we have tests for the case where NewElen is less than 8?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154687/new/

https://reviews.llvm.org/D154687