[llvm] 103df54 - Fix shr/and pair replace with bfe

[Luke Drummond via llvm-commits]

Author: Georgi Mirazchiyski
Date: 2023-07-11T14:43:35+01:00
New Revision: 103df542b54d5c443f83b8e23f619f33d4a42190

URL: https://github.com/llvm/llvm-project/commit/103df542b54d5c443f83b8e23f619f33d4a42190
DIFF: https://github.com/llvm/llvm-project/commit/103df542b54d5c443f83b8e23f619f33d4a42190.diff

LOG: Fix shr/and pair replace with bfe

Co-Authored-By: Aidan Belton <aidan.belton at codeplay.com>
Reviewed By: tra
Differential Revision: https://reviews.llvm.org/D117118

Added: 
    

Modified: 
    llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
    llvm/test/CodeGen/NVPTX/bfe.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
index db69431cceefcd..99a7fdb9d1e21f 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
@@ -3297,7 +3297,7 @@ bool NVPTXDAGToDAGISel::tryBFE(SDNode *N) {
     }
 
     // How many bits are in our mask?
-    uint64_t NumBits = llvm::countr_one(MaskVal);
+    int64_t NumBits = countr_one(MaskVal);
     Len = CurDAG->getTargetConstant(NumBits, DL, MVT::i32);
 
     if (LHS.getOpcode() == ISD::SRL || LHS.getOpcode() == ISD::SRA) {
@@ -3309,7 +3309,7 @@ bool NVPTXDAGToDAGISel::tryBFE(SDNode *N) {
         uint64_t StartVal = StartConst->getZExtValue();
         // How many "good" bits do we have left?  "good" is defined here as bits
         // that exist in the original value, not shifted in.
-        uint64_t GoodBits = Start.getValueSizeInBits() - StartVal;
+        int64_t GoodBits = Start.getValueSizeInBits() - StartVal;
         if (NumBits > GoodBits) {
           // Do not handle the case where bits have been shifted in. In theory
           // we could handle this, but the cost is likely higher than just

diff  --git a/llvm/test/CodeGen/NVPTX/bfe.ll b/llvm/test/CodeGen/NVPTX/bfe.ll
index 58449a74dd6c3a..4acd5e99fb0ac6 100644
--- a/llvm/test/CodeGen/NVPTX/bfe.ll
+++ b/llvm/test/CodeGen/NVPTX/bfe.ll
@@ -31,3 +31,37 @@ define i32 @bfe2(i32 %a) {
   %val1 = and i32 %val0, 7
   ret i32 %val1
 }
+
+; CHECK-LABEL: no_bfe_on_32bit_overflow
+define i32 @no_bfe_on_32bit_overflow(i32 %a) {
+; CHECK-NOT: bfe.u32 %r{{[0-9]+}}, %r{{[0-9]+}}, 31, 4
+  %val0 = ashr i32 %a, 31
+  %val1 = and i32 %val0, 15
+  ret i32 %val1
+}
+
+; CHECK-LABEL: no_bfe_on_32bit_overflow_shr_and_pair
+define i32 @no_bfe_on_32bit_overflow_shr_and_pair(i32 %a) {
+; CHECK: shr.s32 %r{{[0-9]+}}, %r{{[0-9]+}}, 31
+; CHECK: and.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, 15
+  %val0 = ashr i32 %a, 31
+  %val1 = and i32 %val0, 15
+  ret i32 %val1
+}
+
+; CHECK-LABEL: no_bfe_on_64bit_overflow
+define i64 @no_bfe_on_64bit_overflow(i64 %a) {
+; CHECK-NOT: bfe.u64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, 63, 3
+  %val0 = ashr i64 %a, 63
+  %val1 = and i64 %val0, 7
+  ret i64 %val1
+}
+
+; CHECK-LABEL: no_bfe_on_64bit_overflow_shr_and_pair
+define i64 @no_bfe_on_64bit_overflow_shr_and_pair(i64 %a) {
+; CHECK: shr.s64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, 63
+; CHECK: and.b64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, 7
+  %val0 = ashr i64 %a, 63
+  %val1 = and i64 %val0, 7
+  ret i64 %val1
+}