[llvm] 82458ce - [ARM] mark tMOVi32imm as killing flags

[Simon Wallis via llvm-commits]

Author: Simon Wallis
Date: 2023-07-11T14:42:07+01:00
New Revision: 82458ce69eb0de27b6b794974a618fb058f8af45

URL: https://github.com/llvm/llvm-project/commit/82458ce69eb0de27b6b794974a618fb058f8af45
DIFF: https://github.com/llvm/llvm-project/commit/82458ce69eb0de27b6b794974a618fb058f8af45.diff

LOG:  [ARM] mark tMOVi32imm as killing flags

Mark the tMOVi32imm pseudo instr as killing the flags register.

The pseudo instruction expands to a sequence of 7 movs/lsls/adds
instructions, which are all Thumb-1 flag setting instructions.

For a test case, take an existing arm test which checks for
"Don't CSE a cmp across a call that clobbers CPSR."
and retarget it at thumbv6m execute-only.

Reviewed By: stuij

Differential Revision: https://reviews.llvm.org/D154845

Change-Id: I8f8209fbc40a833f8875629937b9606c1e2c021d

Added: 
    

Modified: 
    llvm/lib/Target/ARM/ARMInstrThumb.td
    llvm/test/CodeGen/ARM/cse-call.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td
index f20e81d5d9f341..df6c129a185731 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb.td
@@ -1609,7 +1609,7 @@ def tLDRLIT_ga_abs : PseudoInst<(outs tGPR:$dst), (ins i32imm:$src),
 // relocations.
 // This is a single pseudo instruction to make it re-materializable.
 // FIXME: Remove this when we can do generalized remat.
-let isReMaterializable = 1, isMoveImm = 1, Size = 16, hasNoSchedulingInfo = 1 in
+let Defs = [CPSR], isReMaterializable = 1, isMoveImm = 1, Size = 16, hasNoSchedulingInfo = 1 in
 def tMOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), NoItinerary,
                             [(set rGPR:$dst, (i32 imm:$src))]>,
                             Requires<[IsThumb1Only, GenExecuteOnly, DontUseMovt]>;

diff  --git a/llvm/test/CodeGen/ARM/cse-call.ll b/llvm/test/CodeGen/ARM/cse-call.ll
index 3fc935bb321d31..71cfa3b9da9302 100644
--- a/llvm/test/CodeGen/ARM/cse-call.ll
+++ b/llvm/test/CodeGen/ARM/cse-call.ll
@@ -1,10 +1,29 @@
-; RUN: llc < %s -mcpu=arm1136jf-s -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=armv6-apple-ios0.0.0 -mcpu=arm1136jf-s -verify-machineinstrs | FileCheck %s
+; RUN: llc -mtriple=thumbv6m-eabi -mattr=+execute-only -verify-machineinstrs %s -o - | FileCheck --check-prefix=CHECK-T1 %s
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
-target triple = "armv6-apple-ios0.0.0"
 
 ; Don't CSE a cmp across a call that clobbers CPSR.
 ;
 ; CHECK: cmp
+
+; CHECK-T1: movs [[REG:r[0-7]+]], :upper8_15:
+; CHECK-T1-NEXT: lsls    [[REG]], [[REG]], #8
+; CHECK-T1-NEXT: adds    [[REG]], :upper0_7:
+; CHECK-T1-NEXT: lsls    [[REG]], [[REG]], #8
+; CHECK-T1-NEXT: adds    [[REG]], :lower8_15:
+; CHECK-T1-NEXT: lsls    [[REG]], [[REG]], #8
+; CHECK-T1-NEXT: adds    [[REG]], :lower0_7:
+
+; CHECK-T1: movs [[REG:r[0-7]+]], :upper8_15:
+; CHECK-T1-NEXT: lsls    [[REG]], [[REG]], #8
+; CHECK-T1-NEXT: adds    [[REG]], :upper0_7:
+; CHECK-T1-NEXT: lsls    [[REG]], [[REG]], #8
+; CHECK-T1-NEXT: adds    [[REG]], :lower8_15:
+; CHECK-T1-NEXT: lsls    [[REG]], [[REG]], #8
+; CHECK-T1-NEXT: adds    [[REG]], :lower0_7:
+
+; CHECK-T1: cmp
+
 ; CHECK: S_trimzeros
 ; CHECK: cmp
 ; CHECK: strlen