[PATCH] D154756: [AArch64] Add scheduling model for Neoverse V1

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Looks like another good addition. Thanks for working on this.



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Comment at: llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td:29
+
+  list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F, [HasMTE]);
+}
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Does it help to add SVE2 too?


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Comment at: llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td:58
+                              V1UnitM0, V1UnitM1]>;   // Integer units
+def V1UnitJ   : ProcResGroup<[V1UnitS, V1UnitM0]>;    // Integer 0-2 units
+def V1UnitM   : ProcResGroup<[V1UnitM0, V1UnitM1]>;   // Integer multicycle units
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J is invented to model the instructions that set flags, that have a throughput of 3?


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Comment at: llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td:471
+// COPY
+def : SchedAlias<WriteI, V1Write_1c_1I>;
+def : InstRW<[WriteI], (instrs COPY)>;
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These are mostly ALU instructions.


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Comment at: llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-neon-instructions.s:22
+addp v0.8b, v0.8b, v0.8b
+and v0.8b, v0.8b, v0.8b
+bic v0.4h, #15, lsl #8
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The Neoverse-V2 version of this file has some extra instructions like addv's, aes and some dup instructions, among others.


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  https://reviews.llvm.org/D154756/new/

https://reviews.llvm.org/D154756