[PATCH] D154744: [RISCV] Don't allow X0 to be used for 'r' constraint in inline assembly
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 10 13:30:44 PDT 2023
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGdbd47c4489b1: [RISCV] Don't allow X0 to be used for 'r' constraint in inline assembly (authored by craig.topper).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D154744/new/
https://reviews.llvm.org/D154744
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/inline-asm.ll
Index: llvm/test/CodeGen/RISCV/inline-asm.ll
===================================================================
--- llvm/test/CodeGen/RISCV/inline-asm.ll
+++ llvm/test/CodeGen/RISCV/inline-asm.ll
@@ -29,6 +29,33 @@
ret i32 %2
}
+; Don't allow 'x0' for 'r'. Some instructions have a different behavior when
+; x0 is encoded.
+define i32 @constraint_r_zero(i32 %a) nounwind {
+; RV32I-LABEL: constraint_r_zero:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a0, %hi(gi)
+; RV32I-NEXT: lw a0, %lo(gi)(a0)
+; RV32I-NEXT: li a1, 0
+; RV32I-NEXT: #APP
+; RV32I-NEXT: add a0, a1, a0
+; RV32I-NEXT: #NO_APP
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: constraint_r_zero:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a0, %hi(gi)
+; RV64I-NEXT: lw a0, %lo(gi)(a0)
+; RV64I-NEXT: li a1, 0
+; RV64I-NEXT: #APP
+; RV64I-NEXT: add a0, a1, a0
+; RV64I-NEXT: #NO_APP
+; RV64I-NEXT: ret
+ %1 = load i32, ptr @gi
+ %2 = tail call i32 asm "add $0, $1, $2", "=r,r,r"(i32 0, i32 %1)
+ ret i32 %2
+}
+
define i32 @constraint_i(i32 %a) nounwind {
; RV32I-LABEL: constraint_i:
; RV32I: # %bb.0:
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -15845,7 +15845,7 @@
// TODO: Support fixed vectors up to XLen for P extension?
if (VT.isVector())
break;
- return std::make_pair(0U, &RISCV::GPRRegClass);
+ return std::make_pair(0U, &RISCV::GPRNoX0RegClass);
case 'f':
if (Subtarget.hasStdExtZfhOrZfhmin() && VT == MVT::f16)
return std::make_pair(0U, &RISCV::FPR16RegClass);
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D154744.538797.patch
Type: text/x-patch
Size: 1719 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230710/8ff15205/attachment.bin>
More information about the llvm-commits
mailing list