[PATCH] D154744: [RISCV] Don't allow X0 to be used for 'r' constraint in inline assembly

Kito Cheng via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Jul 10 06:47:59 PDT 2023

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kito-cheng added a comment.

FYI: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/45


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154744/new/

https://reviews.llvm.org/D154744

Previous message: [PATCH] D154791: [InstCombine] Transform bitwise (A >> C - 1, zext(icmp)) -> zext (bitwise(A < 0, icmp)) fold.
Next message: [PATCH] D154744: [RISCV] Don't allow X0 to be used for 'r' constraint in inline assembly
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