[PATCH] D154808: [RISCV] Add tests for (and (add x, c1), (lshr y, c2))

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Add tests for (and (add x, c1), (lshr y, c2)).

Signed-off-by: WANG Rui <wangrui at loongson.cn>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D154808

Files:
  llvm/test/CodeGen/RISCV/lsr-legaladdimm.ll


Index: llvm/test/CodeGen/RISCV/lsr-legaladdimm.ll
===================================================================
--- llvm/test/CodeGen/RISCV/lsr-legaladdimm.ll
+++ llvm/test/CodeGen/RISCV/lsr-legaladdimm.ll
@@ -46,3 +46,18 @@
 for.end:
   ret i32 0
 }
+
+define i32 @lsr_addimm(i32 %x, i32 %y) {
+; RV32I-LABEL: lsr_addimm:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a2, 1
+; RV32I-NEXT:    addi a2, a2, -1
+; RV32I-NEXT:    add a0, a0, a2
+; RV32I-NEXT:    srli a1, a1, 20
+; RV32I-NEXT:    and a0, a1, a0
+; RV32I-NEXT:    ret
+  %1 = add i32 %x, 4095
+  %2 = lshr i32 %y, 20
+  %r = and i32 %2, %1
+  ret i32 %r
+}


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