[PATCH] D146121: [DAG] Move lshr narrowing from visitANDLike to SimplifyDemandedBits

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1871
+           TLO.DAG.MaskedValueIsZero(
+               Op0, APInt::getHighBitsSet(BitWidth, BitWidth / 2)))) {
+        EVT HalfVT = EVT::getIntegerVT(*TLO.DAG.getContext(), BitWidth / 2);
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goldstein.w.n wrote:
> Doesn't the `InDemandedMask.countLeadingZeros() >= (BitWidth / 2)` check the same thing as `TLO.DAG.MaskedValueIsZero(Op0, APInt::getHighBitsSet(BitWidth, BitWidth / 2))` What is the rationale for having both?
No, InDemandedMask checks if we don't care about the upper bits at all (i.e. the SRL is used by a truncate or a AND mask like in the original implementation), and the MaskedValueIsZero alternatively checks if the upper bits are already known to be zero, in which case the (free) zext/trunc can preserve those bits correctly, using a more profitable narrower op, and possibly allowing further folds to occur. Removing either will result in test changes.


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  https://reviews.llvm.org/D146121/new/

https://reviews.llvm.org/D146121