[PATCH] D154785: [AVR] Expand all non-8-bit shifts

[Patryk Wychowaniec via Phabricator via llvm-commits]

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Currently our AVRShiftExpand pass expands only 32-bit shifts, with the
assumption that other kinds of shifts (e.g. 16-bit or 64-bit ones) are
automatically reduced to 8-bit ones by LLVM during isel.

As it turns out though, during isel LLVM can generate a large shift
anyway (see the new attached test) and this causes our code to panic
(because we assume that non-8-bit shifts must've been already expanded).

This commit changes the logic a bit, so that instead of expanding only
32-bit shifts, we expand all non-8-bit shifts.

This is not the most optimal thing to do here, because it reduces the
opportunity for optimizations -- following the new test: we'll generate
a 64-bit shift there even though a 32-bit shift would theoretically
suffice (and would be generated, had we merged AVRShiftExpand pass into
the isel pass).

Merging the shift-expansion pass with instruction selection pass is a
much more complicated endeavour though, and so this commit only adjusts
the shift-expansion pass.

I've checked the generated code using rustc + simavr, and all shifts
seem to behave correctly.

Spotted in the wild in rustc:

- https://github.com/rust-lang/compiler-builtins/issues/523
- https://github.com/rust-lang/rust/issues/112140


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D154785

Files:
  llvm/lib/Target/AVR/AVRShiftExpand.cpp
  llvm/test/CodeGen/AVR/shift-expand.ll
  llvm/test/CodeGen/AVR/shift-late-expand.ll
  llvm/test/CodeGen/AVR/shift.ll

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