[PATCH] D154760: [DAGCombine] Canonicalize operands for visitANDLike

hev via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sat Jul 8 06:25:06 PDT 2023


hev added a comment.

Thanks.



================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6126
   // TODO: Rewrite this to return a new 'AND' instead of using CombineTo.
-  if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
-      VT.getSizeInBits() <= 64 && N0->hasOneUse()) {
-    if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
-      if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
+  if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::ADD &&
+      VT.getSizeInBits() <= 64 && N1->hasOneUse()) {
----------------
RKSimon wrote:
> Why are you having to swap all the ADD/SRL operand handling? Can't you just adjust the std::swap code above?
The following has another match `N0 == ISD::SRL`.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6160
   //   (i64 zero_extend (and (srl (i32 (trunc i64:x)), K)), KMask)
   if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
     if (ConstantSDNode *CAnd = dyn_cast<ConstantSDNode>(N1)) {
----------------
Here


Repository:
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  https://reviews.llvm.org/D154760/new/

https://reviews.llvm.org/D154760



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