[PATCH] D154760: [DAGCombine] Canonicalize operands for visitANDLike

[hev via Phabricator via llvm-commits]

hev created this revision.
hev added reviewers: bogner, MatzeB, RKSimon, spatel.
hev added a project: LLVM.
Herald added subscribers: StephenFan, luismarques, steven.zhang, s.egerton, PkmX, simoncook, hiraditya, arichardson.
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Herald added subscribers: llvm-commits, wangpc.

During the construction of SelectionDAG, there are no explicit canonicalization rules to adjust the order of operands for AND nodes.  This may prevent the optimization in DAGCombiner::visitANDLike from being triggered. This patch canonicalizes the operands before matches, which can be observed to improve optimization on the RISC-V target architecture.

  define i32 @test(i32 %x, i32 %y) {
    %1 = add i32 %x, 4095
    %2 = lshr i32 %y, 20
    %r = and i32 %2, %1
    ret i32 %r
  }



  test:
    lui   a2, 1
    addiw a2, a2, -1
    addw  a0, a0, a2
    srliw a1, a1, 20
    and   a0, a1, a0
    ret



>
=

  test:
    addiw a0, a0, -1
    srliw a1, a1, 20
    and   a0, a1, a0
    ret

Signed-off-by: WANG Rui <wangrui at loongson.cn>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D154760

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -6119,11 +6119,14 @@
   if (SDValue V = foldLogicOfSetCCs(true, N0, N1, DL))
     return V;
 
+  if (N1.getOpcode() == ISD::SRL)
+    std::swap(N0, N1);
+
   // TODO: Rewrite this to return a new 'AND' instead of using CombineTo.
-  if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
-      VT.getSizeInBits() <= 64 && N0->hasOneUse()) {
-    if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
-      if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
+  if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::ADD &&
+      VT.getSizeInBits() <= 64 && N1->hasOneUse()) {
+    if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
+      if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
         // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
         // immediate for an add, but it is legal if its top c2 bits are set,
         // transform the ADD so the immediate doesn't need to be materialized
@@ -6134,14 +6137,14 @@
             !TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
           APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
                                              SRLC.getZExtValue());
-          if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
+          if (DAG.MaskedValueIsZero(N1.getOperand(1), Mask)) {
             ADDC |= Mask;
             if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
-              SDLoc DL0(N0);
+              SDLoc DL0(N1);
               SDValue NewAdd =
                 DAG.getNode(ISD::ADD, DL0, VT,
-                            N0.getOperand(0), DAG.getConstant(ADDC, DL, VT));
-              CombineTo(N0.getNode(), NewAdd);
+                            N1.getOperand(0), DAG.getConstant(ADDC, DL, VT));
+              CombineTo(N1.getNode(), NewAdd);
               // Return N so it doesn't get rechecked!
               return SDValue(N, 0);
             }


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