[llvm] 1748694 - [AArch64] Refactor predicate to check for a ZR operand (NFC)

[Evandro Menezes via llvm-commits]

Author: Evandro Menezes
Date: 2023-07-07T19:19:24-05:00
New Revision: 174869447fc6a6cd36079627e2a558a91c4b3a9f

URL: https://github.com/llvm/llvm-project/commit/174869447fc6a6cd36079627e2a558a91c4b3a9f
DIFF: https://github.com/llvm/llvm-project/commit/174869447fc6a6cd36079627e2a558a91c4b3a9f.diff

LOG: [AArch64] Refactor predicate to check for a ZR operand (NFC)

Create generic predicates to check for a ZR among the possible register
operands.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
    llvm/lib/Target/AArch64/AArch64SchedPredExynos.td
    llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td
    llvm/lib/Target/AArch64/AArch64SchedPredicates.td

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
index fd7be6ea61693b..199ebc6ac650cf 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
@@ -948,8 +948,8 @@ def V2Write_IncDec : SchedWriteVariant<[
 def V2Wr_IM   : SchedWriteRes<[V2UnitM]>  { let Latency = 2; }
 def V2Wr_IMA  : SchedWriteRes<[V2UnitM0]> { let Latency = 2; }
 def V2Wr_IMUL : SchedWriteVariant<[
-                  SchedVar<NeoverseReg3IsZero, [V2Wr_IM]>,
-                  SchedVar<NoSchedPred,        [V2Wr_IMA]>]>;
+                  SchedVar<IsReg3ZeroPred, [V2Wr_IM]>,
+                  SchedVar<NoSchedPred,    [V2Wr_IMA]>]>;
 def V2Rd_IMA  : SchedReadAdvance<1, [V2Wr_IMA]>;
 
 def V2Wr_FMA : SchedWriteRes<[V2UnitV]> { let Latency = 4; }

diff  --git a/llvm/lib/Target/AArch64/AArch64SchedPredExynos.td b/llvm/lib/Target/AArch64/AArch64SchedPredExynos.td
index ff0257fa6e65a4..f68fc3675f89b5 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedPredExynos.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedPredExynos.td
@@ -125,12 +125,7 @@ def ExynosResetFn   : TIIPredicate<
                              MCReturnStatement<TruePred>>,
                            MCOpcodeSwitchCase<
                              [ORRWri, ORRXri],
-                             MCReturnStatement<
-                               CheckAll<
-                                 [CheckIsRegOperand<1>,
-                                  CheckAny<
-                                    [CheckRegOperand<1, WZR>,
-                                     CheckRegOperand<1, XZR>]>]>>>],
+                             MCReturnStatement<CheckIsReg1Zero>>],
                           MCReturnStatement<
                             CheckAny<
                               [IsCopyIdiomFn,

diff  --git a/llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td b/llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td
index 8785b479942678..57f82c28ca0e95 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td
@@ -18,14 +18,6 @@ def NeoverseNoLSL : MCSchedPredicate<
                       CheckAll<[CheckShiftLSL,
                                 CheckShiftBy0]>>;
 
-// Check if the fourth operand of an instruction is WZR or XZR
-def NeoverseReg3IsZero : MCSchedPredicate<
-                           CheckAll<
-                             [CheckIsRegOperand<3>,
-                              CheckAny<
-                                [CheckRegOperand<3, WZR>,
-                                 CheckRegOperand<3, XZR>]>]>>;
-
 // Identify LDR/STR H/Q-form scaled (and potentially extended) FP instructions
 def NeoverseHQForm : MCSchedPredicate<
                        CheckAll<[

diff  --git a/llvm/lib/Target/AArch64/AArch64SchedPredicates.td b/llvm/lib/Target/AArch64/AArch64SchedPredicates.td
index 355e35130a97d0..854d3ce564831d 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedPredicates.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedPredicates.td
@@ -59,6 +59,19 @@ let FunctionMapper = "AArch64_AM::getShiftType" in {
 }
 
 // Generic predicates.
+
+// Check for ZR in a register operand.
+foreach I = {1-3} in {
+  def CheckIsReg#I#Zero : CheckAll<
+                            [CheckIsRegOperand<I>,
+                             CheckAny<
+                               [CheckRegOperand<I, WZR>,
+                                CheckRegOperand<I, XZR>]>]>;
+}
+def IsReg1ZeroPred  : MCSchedPredicate<CheckIsReg1Zero>;
+def IsReg2ZeroPred  : MCSchedPredicate<CheckIsReg2Zero>;
+def IsReg3ZeroPred  : MCSchedPredicate<CheckIsReg3Zero>;
+
 // Identify whether an instruction is NEON or floating point
 def CheckFpOrNEON : CheckFunctionPredicateWithTII<
   "AArch64_MC::isFpOrNEON",
@@ -288,11 +301,8 @@ def IsCopyIdiomFn     : TIIPredicate<"isCopyIdiom",
                                           [ORRWrs, ORRXrs],
                                           MCReturnStatement<
                                             CheckAll<
-                                              [CheckIsRegOperand<1>,
+                                              [CheckIsReg1Zero,
                                                CheckIsRegOperand<2>,
-                                               CheckAny<
-                                                 [CheckRegOperand<1, WZR>,
-                                                  CheckRegOperand<1, XZR>]>,
                                                CheckShiftBy0]>>>],
                                        MCReturnStatement<FalsePred>>>;
 def IsCopyIdiomPred   : MCSchedPredicate<IsCopyIdiomFn>;
@@ -305,10 +315,7 @@ def IsZeroIdiomFn     : TIIPredicate<"isZeroIdiom",
                                          [ORRWri, ORRXri],
                                          MCReturnStatement<
                                            CheckAll<
-                                             [CheckIsRegOperand<1>,
-                                              CheckAny<
-                                                [CheckRegOperand<1, WZR>,
-                                                 CheckRegOperand<1, XZR>]>,
+                                             [CheckIsReg1Zero,
                                               CheckZeroOperand<2>]>>>],
                                       MCReturnStatement<FalsePred>>>;
 def IsZeroIdiomPred   : MCSchedPredicate<IsZeroIdiomFn>;
@@ -333,6 +340,6 @@ def IsZeroFPIdiomFn   : TIIPredicate<"isZeroFPIdiom",
 def IsZeroFPIdiomPred : MCSchedPredicate<IsZeroFPIdiomFn>;
 
 // Identify EXTR as the alias for ROR (immediate).
-def IsRORImmIdiomPred : MCSchedPredicate<
+def IsRORImmIdiomPred : MCSchedPredicate< // EXTR Rd, Rs, Rs, #Imm
                           CheckAll<[CheckOpcode<[EXTRWrri, EXTRXrri]>,
                                     CheckSameRegOperand<1, 2>]>>;