[PATCH] D154536: [RISCV] Check for alignment when lowering interleaved/deinterleaved loads/stores

[Luke Lau via Phabricator via llvm-commits]

luke added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll:43
+; CHECK-NEXT:    vwmaccu.vx v12, a1, v10
+; CHECK-NEXT:    vs4r.v v12, (a0)
 ; CHECK-NEXT:    ret
----------------
reames wrote:
> Amusingly, this is still wrong by the alignment rule.
> 
> "Implementations are allowed to raise a misaligned address exception on whole register loads and stores if the base address
> is not naturally aligned to the larger of the size of the encoded EEW in bytes (EEW/8) or the implementation’s smallest
> supported SEW size in bytes (SEW MIN /8)."
> 
> But this has nothing to do with the segment load/store lowering stuff.  
I did a bit of investigating, and I think this might actually be ok after what Craig pointed out in D154739. vsNr.v always has EEW=8, since the MEW bit is 0 and width[2:0] is 0. Admittedly it took me a while to parse this from the spec. And that's what we test for in unaligned-loads-stores.ll anyway


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  https://reviews.llvm.org/D154536/new/

https://reviews.llvm.org/D154536