[llvm] 6f90808 - [RISCV] Add a guard condition to orc_b/brev8 handling in ReplaceNodeResults.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-07-07T08:51:46-07:00
New Revision: 6f90808074c4241775e111d8aca61889b10d8d0a

URL: https://github.com/llvm/llvm-project/commit/6f90808074c4241775e111d8aca61889b10d8d0a
DIFF: https://github.com/llvm/llvm-project/commit/6f90808074c4241775e111d8aca61889b10d8d0a.diff

LOG: [RISCV] Add a guard condition to orc_b/brev8 handling in ReplaceNodeResults.

The orc_b and brev8 intrinsics are type overloaded, but only
i32 and XLen are supported types. The type legalization code in
ReplaceNodeResults only handles the i32 case on RV64. Add some
checks so we will fail type legalization for other types.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 1b79172a69c8eb..abc81541887917 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -9757,6 +9757,8 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
     }
     case Intrinsic::riscv_orc_b:
     case Intrinsic::riscv_brev8: {
+      if (!Subtarget.is64Bit() || N->getValueType(0) != MVT::i32)
+        return;
       unsigned Opc =
           IntNo == Intrinsic::riscv_brev8 ? RISCVISD::BREV8 : RISCVISD::ORC_B;
       SDValue NewOp =