[PATCH] D154535: [RISCV] Add tests for unaligned segmented loads and stores

[Luke Lau via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG18013bea4688: [RISCV] Add tests for unaligned segmented loads and stores (authored by luke).

Changed prior to commit:
  https://reviews.llvm.org/D154535?vs=537444&id=538141#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154535/new/

https://reviews.llvm.org/D154535

Files:
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll
  llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
  llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll


Index: llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
+++ llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
@@ -32,6 +32,18 @@
   ret void
 }
 
+; FIXME: Shouldn't be lowered to vsseg because it's unaligned
+define void @vector_interleave_store_nxv16i16_nxv8i16_align1(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, ptr %p) {
+; CHECK-LABEL: vector_interleave_store_nxv16i16_nxv8i16_align1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
+; CHECK-NEXT:    vsseg2e16.v v8, (a0)
+; CHECK-NEXT:    ret
+  %res = call <vscale x 16 x i16> @llvm.experimental.vector.interleave2.nxv16i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
+  store <vscale x 16 x i16> %res, ptr %p, align 1
+  ret void
+}
+
 define void @vector_interleave_store_nxv16i16_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, ptr %p) {
 ; CHECK-LABEL: vector_interleave_store_nxv16i16_nxv8i16:
 ; CHECK:       # %bb.0:
Index: llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
+++ llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
@@ -39,6 +39,18 @@
   ret {<vscale x 16 x i8>, <vscale x 16 x i8>} %retval
 }
 
+; FIXME: Shouldn't be lowered to vlseg because it's unaligned
+define {<vscale x 8 x i16>, <vscale x 8 x i16>} @vector_deinterleave_load_nxv8i16_nxv16i16_align1(ptr %p) {
+; CHECK-LABEL: vector_deinterleave_load_nxv8i16_nxv16i16_align1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
+; CHECK-NEXT:    vlseg2e16.v v8, (a0)
+; CHECK-NEXT:    ret
+  %vec = load <vscale x 16 x i16>, ptr %p, align 1
+  %retval = call {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.experimental.vector.deinterleave2.nxv16i16(<vscale x 16 x i16> %vec)
+  ret {<vscale x 8 x i16>, <vscale x 8 x i16>} %retval
+}
+
 define {<vscale x 8 x i16>, <vscale x 8 x i16>} @vector_deinterleave_load_nxv8i16_nxv16i16(ptr %p) {
 ; CHECK-LABEL: vector_deinterleave_load_nxv8i16_nxv16i16:
 ; CHECK:       # %bb.0:
Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll
+++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll
@@ -29,6 +29,18 @@
   ret void
 }
 
+; FIXME: Shouldn't be lowered to vsseg because it's unaligned
+define void @vector_interleave_store_v16i16_v8i16_align1(<8 x i16> %a, <8 x i16> %b, ptr %p) {
+; CHECK-LABEL: vector_interleave_store_v16i16_v8i16_align1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vsseg2e16.v v8, (a0)
+; CHECK-NEXT:    ret
+  %res = call <16 x i16> @llvm.experimental.vector.interleave2.v16i16(<8 x i16> %a, <8 x i16> %b)
+  store <16 x i16> %res, ptr %p, align 1
+  ret void
+}
+
 define void @vector_interleave_store_v16i16_v8i16(<8 x i16> %a, <8 x i16> %b, ptr %p) {
 ; CHECK-LABEL: vector_interleave_store_v16i16_v8i16:
 ; CHECK:       # %bb.0:
Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
+++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
@@ -82,6 +82,18 @@
   ret {<16 x i8>, <16 x i8>} %retval
 }
 
+; FIXME: Shouldn't be lowered to vlseg because it's unaligned
+define {<8 x i16>, <8 x i16>} @vector_deinterleave_load_v8i16_v16i16_align1(ptr %p) {
+; CHECK-LABEL: vector_deinterleave_load_v8i16_v16i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vlseg2e16.v v8, (a0)
+; CHECK-NEXT:    ret
+  %vec = load <16 x i16>, ptr %p, align 1
+  %retval = call {<8 x i16>, <8 x i16>} @llvm.experimental.vector.deinterleave2.v16i16(<16 x i16> %vec)
+  ret {<8 x i16>, <8 x i16>} %retval
+}
+
 define {<8 x i16>, <8 x i16>} @vector_deinterleave_load_v8i16_v16i16(ptr %p) {
 ; CHECK-LABEL: vector_deinterleave_load_v8i16_v16i16:
 ; CHECK:       # %bb.0:


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