[PATCH] D154533: [DAG] Improve carry reconstruction in combineCarryDiamond.

[Sergei Barannikov via Phabricator via llvm-commits]

barannikov88 added a comment.

> In this case, we replace a complex web of instructions by just one add. Reconstructing a carry is worth it. The test cases that were changed bellow are good exemple of that, the carry is passed as an argument to the functions, so it is not possible to know if these are "real" carries or not, and it is nevertheless worth doing the transform.

I was thinking about cases like feeding uaddo by a setcc, but that does not seem to pay off. E.g.:

  declare { i64, i1 } @llvm.usub.with.overflow.i64(i64, i64)
  
  define { i64, i1 } @subcarry_fake_carry(i64 %a, i64 %b, i32 %x, i32 %y) {
      %t1 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
      %partial = extractvalue { i64, i1 } %t1, 0
      %k1 = extractvalue { i64, i1 } %t1, 1
  
      %carryin = icmp eq i32 %x, %y
      %zcarryin = zext i1 %carryin to i64
      %s = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %partial, i64 %zcarryin)
      %k2 = extractvalue { i64, i1 } %s, 1
  
      %carryout = or i1 %k1, %k2
  
      %ret = insertvalue { i64, i1 } %s, i1 %carryout, 1
      ret { i64, i1 } %ret
  }

$ llc test.ll -o - -x86-asm-syntax=intel
Before this patch:

  mov     rax, rdi
  sub     rax, rsi
  setb    sil
  xor     edi, edi
  cmp     edx, ecx
  sete    dil
  sub     rax, rdi
  setb    dl
  or      dl, sil

with this patch:

  mov     rax, rdi
  cmp     edx, ecx
  sete    cl
  add     cl, -1
  sbb     rax, rsi
  setb    dl

With my suggestion:

  mov     rax, rdi
  xor     edi, edi
  cmp     edx, ecx
  sete    dil
  add     rdi, -1
  sbb     rax, rsi
  setb    dl


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154533/new/

https://reviews.llvm.org/D154533